PCI IP Core PCI-TMF 32-bit, 33 MHz Multifunction Target Interface Core
On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables
The PCI-TMF implements a target-only PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz (PCI clock).
The core offers one to eight independent PCI functions in a single chip, each implementing 64 to 256 bytes of PCI Configuration Space registers as required. Each function supports up to six Base Address Registers, with both I/O and Memory space decoding from 16 bytes up to 4GB.
The core was developed for easy reuse with ASICs or FPGAs.
See representative implementation results (each in a new pop-up window):
Features
- Fully compliant with the PCI Local Bus Specification, Revision 2.3.
- 33 MHz performance (PCI clock frequency)
- 32-bit datapath
- Full Target functionality, with support for these commands:
- Configuration Read, Configuration Write
- Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL), Memory Write and Invalidate (MWI)
- I/O Read, I/O Write
- Zero wait states burst mode
- Support all interrupt pins (INTA#, INTB#, INTC#, INTD#)
- Type 0 Configuration space
- Supports all Base Address Registers
- Supports backend initiated target retry, disconnect and abort
- Parity generation and parity error detection
- Silicon-verified (XILINX Virtex FPGA)
- PC300 prototyping board available for fast application prototyping
Applications
- PCI I/O communication boards
- PCI Data Acquisition Boards
- Embedded system PCI applications
Symbol Diagram
Block Diagram
The following diagram illustrates how the multi-function PCI-TMF core might interface with multiple user applications.
Typical architecture for multiple PCI/application interfaces
Functional Description
As shown in the block diagram and explained below, the PCI-TMF32 includes five major blocks: Parity Generator, Parity Checker, up to eight Configuration Spaces, Interrupt control, Command Register and Address Counter block, Target State Machine.
Parity Generator
The parity generator generates parity during read transaction.
Parity Checker
The parity checker checks parity during command phase and write transaction.
Configuration Spaces
The PCI-TMF contains up to eight configuration spaces depending on the core setup. Configuration space register block implements the mandatory 64 bytes of PCI Configuration Space registers.
Command Register and Address Counter block
Command Register saves a transaction command at the beginning of PCI transaction. Address Counter block generates a backend address. Address counter is controlled by Target FSM.
Target FSM
Target State Machine is a control block of the PCI-TMF interface. The state machine is in charge of handling PCI transactions protocol.
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench including vectors and expected results
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables
Download PDF datasheets for more info: ASIC | Altera | Xilinx
