PCI IP Core PCI-T64 64-bit, 66 MHz PCI Target Interface Core

The main purpose of the PCI-T64 Interface Core is to isolate the user from having to solve complex problems of PCI interface implementation and let the user focus on the application development.

The PCI-T64 Interface supports a 64-bit address/data bus and operates at up to a 66MHz (PCI clock frequency). It is fully compliant with the PCI Local Bus Specification, Revision 2.3.

The Target supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 4GB.

Target supported commands are:

• Configuration Read, Configuration Write
• Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL),
• I/O Read, I/O Write

See representative implementation results (each in a new pop-up window):

Applications

• PCI I/O communication boards
• PCI Data Acquisition Boards
• Embedded system PCI applications

Symbol Diagram

Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide