- Fully compliant with the PCI Local Bus Specification, Revision 2.3.
- 33 MHz performance (PCI clock frequency)
- 32-bit datapath
- Full Target functionality, with support for these commands:
- Configuration Read, Configuration Write
- Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL), Memory Write and Invalidate (MWI)
- I/O Read, I/O Write
- Zero wait states burst mode
- Support all interrupt pins (INTA#, INTB#, INTC#, INTD#)
- Type 0 Configuration space
- Supports all Base Address Registers
- Supports backend initiated target retry, disconnect and abort
- Parity generation and parity error detection
- Silicon-verified (XILINX Virtex FPGA)
- PC300 prototyping board available for fast application prototyping
Call or click.
- PCI-T32 32-bit, 33 MHz PCI Target Interface
- PCI-T64 64-bit, 66 MHz PCI Target Interface
- PCI-M32 32-bit, 33 MHz PCI Master/Target Interface
- PCI-M32MF Multi-Function PCI Master/Target Interface
- PCI-M64 64-bit, 66 MHz PCI Master/Target Interface
- PCI-HB 32-bit/33,66Mhz PCI Host Bridge
- PCI-DHB-AHB PCI - AMBA AHB Device/Host Bridge Core
- PCI-HB-AHB PCI to AMBA AHB Host Bridge Core
PCI IP Core PCI-T32MF 32-bit, 33 MHz Multifunction Target Interface Core
The PCI-T32MF implements a target-only PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz (PCI clock).
The core offers one to eight independent PCI functions in a single chip, each implementing 64 to 256 bytes of PCI Configuration Space registers as required. Each function supports up to six Base Address Registers, with both I/O and Memory space decoding from 16 bytes up to 4GB.
The core was developed for easy reuse with ASICs or FPGAs.
See representative implementation results (each in a new pop-up window):
- PCI I/O communication boards
- PCI Data Acquisition Boards
- Embedded system PCI applications
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive simulation and rigorous code coverage measurements.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench including vectors and expected results
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide