PCI IP Core PCI-T32 32-bit, 33 MHz PCI Target Interface Core
On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables
The main PCI-T32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on the application development.
The PCI-T32 Interface supports 32-bit address/data bus and operates up to 33 MHz (66 MHz optional) PCI clock frequency. It is fully compliant with the PCI Local Bus Specification, Revision 2.3.
The PCI-T32 Interface is a Target–only PCI Interface core. The interface implements 64 bytes of PCI Configuration Space registers. It is possible to extend the Configuration Space up to 256 bytes if required.
The Target supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 4 GB.
The Target supported commands are:
- Configuration Read, Configuration Write
- Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL), Memory Write and Invalidate (MWI)
- I/O Read, I/O Write
See representative implementation results (each in a new pop-up window):
Features
- Flexible synthesizable VHDL core
- PCI specification 2.3 compliant
- 33 MHz performance (66MHz optional)
- 32-bit datapath
- Zero wait states burst mode
- Full Target functionality
- Single interrupt support
- Type 0 Configuration space
- Support of all Base Address Registers
- Support of backend initiated target retry, disconnect and abort
- Parity generation and parity error detection
- Available in synthesizable VHDL source code
Applications
- PCI I/O communication boards
- PCI Data Acquisition Boards
- Embedded system PCI applications
Symbol Diagram
Block Diagram
Functional Description
As shown in the block diagram and explained below, the PCI-T32 includes five major blocks: Parity Generator, Parity Checker, Configuration Space Registers, Command Register and Address Counter block, Target State Machine.
Parity Generator
The parity generator generates parity during read transaction.
Parity Checker
The parity checker checks parity during command phase and write transaction.
Configuration Space Registers
Configuration Space Registers block implements the mandatory 64 bytes of PCI Configuration Space registers. See the chapter PCI Configuration Space for more details.
Command Register and Address Counter block
Command Register saves a transaction command at the beginning of PCI transaction. Address Counter block generates a backend address. Address counter is controlled by Target FSM.
Target FSM
Target State Machine is a control block of the PCI-T32 interface. The state machine is in charge of handling PCI transactions protocol
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables
Download PDF datasheets for more info: ASIC | Xilinx
