Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Peripheral Platforms
& AMBA Infrastructure

BA2x AHB Platform
BA2x AXI Platform


GPUs & Peripherals
See Graphics &
  Peripherals Cores >

These video and image compression cores and subsystems help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
J2K Platform

Lossless Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Complement or replace system processors with GPUs and easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Graphics Processors
Nema Embedded GPU
ThinkVG vector GPU
2D/2.5D Graphic Accelerator

Display Controllers
Multilayer LCD Display Processor

Device Controllers
smart card reader

Legacy Peripherals
DMA Controllers
8237, 82380
16450S, 16550S, 16750S

AMBA Infrastructure
AMBA Infrastructure Cores
AHB 32-bit DMA

Interconnect Peripherals

See Interconnect Cores >

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

• Receiver

Ethernet MAC
• 1G eMAC Controller

Data Link Controllers

PCI — Target
32-bit multi
PCI — Master
32-bit multi
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

DES single
DES triple

  • PCI specification 2.3 compliant
  • 33 MHz performance (66MHz optional)
  • 32-bit datapath
  • Zero wait states burst mode
  • Full Target functionality
  • Single interrupt support
  • Type 0 Configuration space
  • Support of all Base Address Registers
  • Support of backend initiated target retry, disconnect and abort
  • Parity generation and parity error detection
  • Optional bridge / interface to AMBA/AHB or Avalon-MM
  • Available in synthesizable HDL source code or as targeted FPGA netlist

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PDF Datasheets


Related Products


  • PCI-T32MF 32-bit, 33 MHz Multifunction Target Interface
  • PCI-T64 64-bit, 66 MHz PCI Target Interface
  • PCI-M32 32-bit, 33 MHz PCI Master/Target Interface
  • PCI-M32MF Multi-Function PCI Master/Target Interface
  • PCI-M64 64-bit, 66 MHz PCI Master/Target Interface
  • PCI-HB 32-bit/33,66Mhz PCI Host Bridge
  • PCI-DHB-AHB PCI - AMBA AHB Device/Host Bridge Core
  • PCI-HB-AHB PCI to AMBA AHB Host Bridge Core

Related Information

Validated for Mentor Graphics Presicision FPGA SynthesisValidated for Precision™ FPGA Synthesis

PCI-T32 32-bit, 33 MHz PCI Target Interface Core

The main PCI-T32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on the application development.

The PCI-T32 Interface supports 32-bit address/data bus and operates up to 33 MHz (66 MHz optional) PCI clock frequency. It is fully compliant with the PCI Local Bus Specification, Revision 2.3.

The PCI-T32 Interface is a Target–only PCI Interface core. The interface implements 64 bytes of PCI Configuration Space registers. It is possible to extend the Configuration Space up to 256 bytes if required.

The Target supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 4 GB.

The Target supported commands are:

See representative implementation results (each in a new pop-up window):

Xilinx numbers


Symbol Diagram

PCI-T32 32-bit, 33 MHz PCI Target Interface Symbol Diagram

Block Diagram

PCI-T32 32-bit, 33 MHz PCI Target Interface Block Diagram


The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.


The core has been verified through extensive simulation and rigorous code coverage measurements.


The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation: