Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.
   Stack

IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

  • PCI specification 2.3 compliant
  • 33 MHz performance (66 MHz optional)
  • 32-bit datapath
  • Zero wait states burst mode
  • Full bus Master/Target functionality
  • Single interrupt support
  • Type 0 Configuration space
  • Support of all Base Address Registers
  • Support of backend initiated target retry, disconnect and abort
  • Parity generation and parity error detection
  • DMA Controller Core supporting independent write and read operations available
  • Optional bridge / interface to AMBA/AHB or Avalon-MM
  • Available in synthesizable HDL source code or targeted FPGA netlist

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

Compare
Versions

  • PCI-T32 32-bit, 33 MHz PCI Target Interface
  • PCI-T32MF 32-bit, 33 MHz Multifunction Target Interface
  • PCI-T64 64-bit, 66 MHz PCI Target Interface
  • PCI-M32MF Multi-Function PCI Master/Target Interface
  • PCI-M64 64-bit, 66 MHz PCI Master/Target Interface
  • PCI-HB 32-bit/33,66Mhz PCI Host Bridge
  • PCI-DHB-AHB PCI - AMBA AHB Device/Host Bridge Core
  • PCI-HB-AHB PCI to AMBA AHB Host Bridge Core

PCI-M32 32-bit, 33 MHz PCI Master/Target Interface Core

The main PCI-M32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on the application development.

The PCI-M32 Interface supports 32-bit address/data bus and operates up to 33 MHz (66 MHz optional) PCI clock frequency. It is fully compliant with the PCI Local Bus Specification, Revision 2.3.

The PCI-M32 Interface has both Master and Target capabilities. The interface implements 64 bytes of PCI Configuration Space registers. It is possible to extend the Configuration Space up to 256 bytes if required.

The Target part supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 2 GB. Both Target and Master supported commands are:

The PCI-M32 is designed for reuse in ASIC or FPGA implementations.

This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):

ASIC numbers Microsemi numbers Altera numbers Xilinx numbers

Applications

Symbol Diagram

PCI-M32 32-bit, 33 MHz PCI Master/Target Interface Symbol Diagram

Block Diagram

PCI-M32 32-bit, 33 MHz PCI Master/Target Interface Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

Comparing PCI Cores Family

 

PCI-T32

PCI-T64

PCI-T32MF

PCI-M32

PCI-M64

PCI-M32MF

PCI-HB

PCI-HB-AHB

PCI-DHB-AHB

PCI 33/66 MHz

included

included

included

included included included included included

included

Host

not supported

not supported

not supported

not supported not supported not supported included included

included

Master

not supported

not supported

not supported

included included included not supported not supported

included

Target

included

included

included

included included included not supported not supported

included

Multifunction

not supported

not supported

included

not supported not supported included not supported not supported

not supported

32bit

included

included

included

included included included included included

included

64bit

not supported

included

not supported

not supported included not supported not supported not supported

not supported

SoC Interface

Generic
AXI, AHB,
Avalon-MM1

Generic
AXI, AHB,
Avalon-MM1

Generic
AXI, AHB,
Avalon-MM1

Generic
AHB, AXI,
Avalon-MM1

Generic
AHB, AXI,
Avalon-MM1

Generic
AXI, AHB,
Avalon-MM1

Generic
AXI,
Avalon-MM1

AHB

AHB

ASIC Support

included

included

included

included included included included included

included

FPGA Support

included2

included2

included2

included2 included2 included2 included2 included2

included2

Notes:

included: Feature is supported.
included: Feature optionally supported
not supported: Feature is not supported
 1 : SoC interface in grey font can be made available upon request
 2 : SoC FPGA devices that do not support PCI I/O standard (e.g. Xilinx Virtex-6/7 and Stratix-V) are not supported

 

 

 

PCI I/O Standard Support In FPGA Families

 

 

33MHz PCI

66MHz PCI

xilinx

Spartan-3

included

not supported

Spartan-6 included not supported

Spartan-7

included

not supported

Virtex-5

included

included1

Viretx-6

not supported

not supported

Viretx-7

not supported

not supported

Kintex-7

included

not supported

Artix-7

included

not supported

Kintex UltraScale

not supported

not supported

Altera

Cyclone-III

included

not supported

Cyclone-IV

included

not supported

Cyclone -V

included included1
Cyclone-10LP included not supported

Stratix-III

included included1

Stratix-IV

included included1

Stratix-V

not supported not supported
Stratix-10 not supported not supported

Arria-V

included

included1

Arria-10 not supported not supported
MAX-10 included not supported
Notes:

included) Family supports PCI I/O Standard.
not supported) Family does not support PCI I/O Standard.
 1 ) Evaluation for an exact part and package required.

 

 

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