- PCI specification 2.3 compliant
- 33/66 MHz performance
- 32-bit datapath
- PCI reset generator
- PCI bus arbiter (up to 7 external bus agents)
- Interrupt controller
- Parity generation and parity error detection.
- Dual-port based shared memory
- PCI Configuration registers accessible from both PCI and host directions
- Available in synthesizable VHDL source code
Contact Sales
Call or click.
+1 800.391.8300
PDF Datasheets
Related Products
- PCI-T32 32-bit, 33 MHz PCI Target Interface
- PCI-T32MF 32-bit, 33 MHz Multifunction Target Interface
- PCI-T64 64-bit, 66 MHz PCI Target Interface
- PCI-M32 32-bit, 33 MHz PCI Master/Target Interface
- PCI-M32MF Multi-Function PCI Master/Target Interface
- PCI-M64 64-bit, 66 MHz PCI Master/Target Interface
- PCI-DHB-AHB PCI - AMBA AHB Device/Host Bridge Core
- PCI-HB-AHB PCI to AMBA AHB Host Bridge Core
- MAC-PCI Ethernet MAC Controller with PCI Host Interface
Related Information
PCI Host Bridge IP Core PCI-HB 32-bit/33,66Mhz PCI Host Bridge Core
The PCI Host Bridge core enables data transfers between a host processor system and PCI bus based devices. The bridge is in charge of PCI bus arbitration, generating PCI clock and reset signals. An important part of the bridge is the bus arbiter.
The PCI-HB core is a generic core, which provides all the essential bridge functions without a host bus interface.
See representative PCI-HB implementation results (each in a new pop-up window):
Applications
- PCI-AMBA host bridge
- PCI-CoreConnect bus host bridge
- Embedded system PCI applications
Symbol Diagram
Block Diagram
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs) for PCI-HB
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs) for DMA Controller
- Sophisticated HDL Testbench
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
Share this page: