Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

PCI Host Bridge

  • Enables data communication between the Host Processor residing on an AHB bus and devices on the PCI bus
  • PCI I/O space and memory space are mapped directly to the AMBA AHB memory space
  • PCI Interrupt and System Errors are propagated as interrupts to the host
  • PCI Configuration registers are accessible from both PCI and host directions
  • Advanced PCI data prefetching and AHB data buffering for improved bus bandwidth utilization
  • Asynchronous AMBA/AHB and PCI clocks

PCI Interface

  • PCI specification 3.0 and 2.3 compliant
    • 33/66 MHz
    • 32-bit bus width
    • 32-bit address space
    • Parity generation and parity error detection
  • PCI Master & Target support all types of transactions:
    • Configuration space read/write
    • Memory space read/write
    • I/O Space read/write
    • Interrupt acknowledge (optional)
    • Special cycles (optional)
  • PCI reset generator
  • PCI bus arbiter
    • Up to 7 external bus agents
    • Flexible priority schemes
    • Agent malfunction detection and reporting

AHB Interface

  • 32-bit AMBA/AHB v2.0 host interface
  • AHB Slave enables host to initiated PCI transaction and access configuration registers
  • AHB Master delivers data from the PCI target interface to the host

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

Compare
Versions

  • PCI-HB 32-bit/33,66Mhz PCI Host Bridge Core
  • PCI-DHB-AHB PCI - AMBA AHB Device/Host Bridge Core
  • PCI-T32 32-bit, 33 MHz PCI Target Interface
  • PCI-T32MF 32-bit, 33 MHz Multifunction Target Interface
  • PCI-T64 64-bit, 66 MHz PCI Target Interface
  • PCI-M32 32-bit, 33 MHz PCI Master/Target Interface
  • PCI-M32MF Multi-Function PCI Master/Target Interface
  • PCI-M64 64-bit, 66 MHz PCI Master/Target Interface

PCI-HB-AHB PCI to AMBA AHB Host Bridge Core

This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices.

The bridge enables higher utilization of the bus’ available bandwidth by prefetching PCI data and buffering AHB data, and allows the host to initiate PCI accesses or to respond to transactions initiated by other PCI devices.

The core complies with the PCI bus specification versions 3.0 and 2.3, and can act as a PCI master and target. Furthermore it implements PCI bus arbitration, supporting up to seven PCI bus agents, PCI reset signal generation, and all types of PCI transactions provisioned by the standard.
The host connects to the bridge via master and slave 32-bit AMBA/AHB bus interfaces. The AHB slave interface allows the host to access the status and control registers and to initiate PCI Transfers, while data from the PCI target is communicated to the host via the AHB master interface.

The PCI-HB-AHB builds on more than 10 years of CAST PCI IP expertise and has been designed for straightforward reuse, with proven design practices that ensure easy integration and smooth technology mapping. The core is available in synthesizable RTL or as a targeted FPGA netlist, and is delivered with everything required for rapid and successful integration and implementation.

See representative implementation results (each in a new pop-up window):

ASIC numbers

Block Diagram

pci-hb-ahb block diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation, rigorous code coverage measurements and it has been proven in FPGA and ASIC designs.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

 

Comparing PCI Cores Family

 

PCI-T32

PCI-T64

PCI-T32MF

PCI-M32

PCI-M64

PCI-M32MF

PCI-HB

PCI-HB-AHB

PCI-DHB-AHB

PCI 33/66 MHz

included

included

included

included included included included included

included

Host

not supported

not supported

not supported

not supported not supported not supported included included

included

Master

not supported

not supported

not supported

included included included not supported not supported

included

Target

included

included

not supported

      not supported not supported

included

Multifunction

not supported

not supported

included

not supported not supported included not supported not supported

not supported

32bit

included

included

included

included included included included included

included

64bit

not supported

included

not supported

not supported included not supported not supported not supported

not supported

SoC Interface

Generic
AXI, AHB,
Avalon-MM1

Generic
AXI, AHB,
Avalon-MM1

Generic
AXI, AHB,
Avalon-MM1

Generic
AHB, AXI,
Avalon-MM1

Generic
AHB, AXI,
Avalon-MM1

Generic
AXI, AHB,
Avalon-MM1

Generic
AXI,
Avalon-MM1

AHB

AHB

ASIC Support

included

included

included

included included included included included

included

FPGA Support

included2

included2

included2

included2 included2 included2 included2 included2

included2

 

PCI I/O Standard Support In FPGA Families

 

 

33MHz PCI

66MHz PCI

xilinx

Spartan-3

included

not supported

Spartan-6

included

not supported

Virtex-5

included

included1

Viretx-6

not supported

not supported

Viretx-7

not supported

not supported

Kintex-7

included

not supported

Artix-7

included

not supported

Altera

Cyclone-III

included

not supported

Cyclone-IV

included

not supported

Cyclone -V

included included1

Stratix-III

included included1

Stratix-IV

included included1

Stratix-V

not supported not supported

Arria-V

included

included1

Notes:

included) Family supports PCI I/O Standard.
not supported) Family does not support PCI I/O Standard.
 1 ) Evaluation for an exact part and package required.

 

 

tw    fbk    li    li    li
Top of Page