Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

SPI Flash memory controller supporting XIP and STR or DTR over single, dual, quad, and octal links.

System Interfaces

  • 32-bit AHB Slave for Register Access
  • 32-bit AHB Slave Execute-in-Place (XIP) for direct bridging of AHB to SPI
  • Interrupt line
  • Sideband DMA interface, for easy integration with external DMA controller
  • XIP configuration pins, enabling use of XIP mode after reset and without prior programming

SPI Master Interface

  • Single, Dual, Quad, and Octal data lines
  • Single Transfer Rate (STR) or Dual Transfer Rate (DTR)
  • 4, 8, 16, or 32 bit word transmissions per SPI data line
  • Full and Half Duplex operation
  • Up to four SPI slaves
  • Programmable serial clock polarity and phase
  • Serial clock is provided by the system, and is totally independent from the AHB clock

Flash Devices Support for XIP

  • Supports de-facto standard for Flash command encoding and all widely used SPI bus configurations
  • Supports Flash devices from all major vendors, including Macronix, Micron, Spansion and Windbond

Deliverables

  • Verilog RTL source coder or targeted FPGA netlist
  • User Documentation
  • Testbench and sample synthesis and simulation scripts

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

  • QSPI-XIP-AHB Quad SPI Bus Controller with XIP, for AHB
  • QSPI-XIP-AXI Quad SPI Bus Controller with XIP, for AXI
  • QSPI-MS Quad-Bit Serial Peripheral Interface Master/Slave
  • SPI-MS Serial Peripheral Interface Master/Slave
  • SPI2AHB SPI to AHB-Lite Bridge
  • PFLASH-CTRL Parallel NOR Flash Controller

More Information

OSPI-XIP-AHB Single, Dual, Quad, & Octal SPI Flash Controller for AHB

The OSPI-XIP-AHB core is a flexible, high-performance, SPI Flash memory controller. It enables AHB bus masters  (e.g. host processors or DMA engines) to access the Flash memory address space using standard AMBA AHB 2.0 transactions, without any software assistance. Furthermore, the controller core is able to exploit the bandwidth that standard and high-performance SPI Flash devices offer.  

SPI Bus IP cores icon at CAST Inc.The controller provides two 32-bit AHB slave interfaces towards the on-chip system, and acts as a master on an SPI bus that can accept up to four slave devices. The first AHB slave interface supports eXecute-In-Place (XIP), meaning that the core acts as an AHB-to-SPI bridge for read transfers. The second AHB slave interface provides access to the core’s control and status registers. The register interface enables low-level control of the SPI master port, enabling the system to perform read or write transactions over the SPI bus.

A sideband DMA signaling port can optionally be used to optimize the data transfers between an AHB master and the OSPI-XIP-AHB core. The core also provides a dedicated interface that can be used to control the XIP mode parameters. This XIP configuration interface can be hardwired or driven by other logic, and enables XIP right after reset and without any programming of the core registers. 

The OSPI-XIP-AHB can efficiently utilize the bandwidth of standard and high-performance SPI Flash devices. It supports single transfer rate (STR) or dual transfer rate (DTR) over single, dual, quad, or octal data lines. The SPI link parameters—such as clock phase and polarity, and the bit-width of SPI transmissions—are fully programmable to ensure operations in all widely used SPI bus configurations. Moreover, the core supports the de-facto standard for the encoding of Flash access commends and allows run-time configuration of the command parameters, enabling operation with Flash devices from all major vendors, including Macronix, Micron, Spansion, and Windbond.

This core has been designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production.

Applications

The OSPI-XIP-AHB can be used in SoC designs storing firmware and or application data to an external SPI Flash device, and that are using an AHB, or AHB-Lite SoC bus.

Block Diagram

OSPI-XIP-AHB Single, Dual, Quad, & Octal SPI Flash Conttroller for AHB IP Core Block Diagram

Related IP Cores

The OSPI-XIP-AHB is part of a group of available AMBA peripheral cores that includes bus infrastructure cores, bus bridges, interface controllers (SPI, I2C, CAN, UARTs, and LIN), timers, a real-time clock, and more.

 

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