MTS-E Core — XILINX FPGA Results

The MTS-E can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Xilinx results using balanced area/speed constraints during synthesis and place and route, while assuming that all core I/Os are routed off-chip. The sample results do not represent the highest speed or smallest area for the core. The sample results do not represent the highest speed or smallest area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Family

Slices

Fmax (MHz)

RAM Blocks

Kintex-7
XC7K325T-2

336

412

2

Virtex-7
XC7VX330T-1

327

314

2

Table 1: MTS-E configured with one input stream channel, no RTP, no TS packet grouping and no Program and ES info support.

Family

Slices

Fmax (MHz)

RAM Blocks

Kintex-7
XC7K325T-2

699

335

5

Virtex-7
XC7VX330T-1

712

260

5

Table 2: MTS-E configured with two input stream channel, RTP, TS packet grouping and no Program and ES info support.

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