MTS-E Core — ASIC Implementation Results

The MTS-E can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. These sample results do not represent the highest speed or smallest area for the core. Please contact CAST to get characterization data for your target configuration and technology.

ASIC
Technology

Eq. NAND2 gates

Fmax (MHz)

Memory Bits

TSMC 65nmG

8,322

612

65,536

TSMC 90nmG

7,714

360

65,536

Table 1: MTS-E configured with one input stream channel, no RTP, no TS packet grouping and no Program and ES info support.

ASIC
Technology

Eq. NAND2 gates

Fmax (MHz)

Memory Bits

TSMC 65nmG

19,096

616

150,016

TSMC 90nmG

17,792

360

150,016

Table 2: MTS-E configured with two input stream channel, RTP, TS packet grouping and no Program and ES info support.

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