MTS-E Core — Intel Implementation Results

The MTS-E can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample Intel pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The sample results do not represent the highest speed or smallest area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Family

ALMs

Fmax (MHz)

Memory Bits

Arria-V
5AGXFB3H4F35C4

678

243

65,536

Cyclone-V
5CEBA7F23C8

673

162

65,536

Stratix-V
5SGSMD4E2H29C3

668

390

65,536

Table 1:MTS-E configured with one input stream channel, no RTP, no TS packet grouping and no Program and ES info support.

 

Family

ALMs

Fmax (MHz)

Memory Bits

Arria-V
5AGXFB3H4F35C4

1,341

214

150,016

Cyclone-V
5CEBA7F23C8

1,330

137

150,016

Stratix-V
5SGSMD4E2H29C3

1,324

337

150,016

Table 2:MTS-E configured with two input stream channel, RTP, TS packet grouping and no Program and ES info support.

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