MPEG Transport Stream Multiplexing & Encapsulation
- Compliant to ISO/IEC 13818-1
- Two input stream channels (additional channels upon request)
- Supports common stream types
- Flexible Encapsulation
- Programmable Packetized Elementary Stream (PES) packet size
- Programmable TS packet group size
- Optional Program Info support
- Optional Elementary Stream Info support
- Software enabled/disabled encapsulation of the MPEG Transport stream in RTP packets
- Standalone, processor-less operation
- AMBA® AXI Interfaces
- AXI4-Lite™ Control/Status register interfaces
- AXI4-Streaming™ interfaces for packet data
- Optional Avalon® SoC bus interface
- Configurable input and output buffers sizes
- The MTS-E can be delivered pre-integrated with:
- Video Encoder cores from CAST
- UDP/IP Hardware Stack from CAST, and eMAC core from Intel, Xilinx, or other third-party
MTS-E MPEG Transport Stream Multiplexing & Encapsulation Engine
The MTS-E core multiplexes and encapsulates audio, video and metadata streams in a single MPEG Transport Stream (TS), and optionally encapsulates the TS packets in Real-Time Transport Protocol (RTP) packets.
Under its default configuration, the MTS-E multiplexing and encapsulation engine supports two input stream channels, e.g., one Audio and one Video. Configurations with more than two input stream channels can be made available upon request.
The output transport stream can be forwarded for local storage or transmitted over an Internet Protocol (IP) or other network. Streaming over IP networks often imposes further encapsulation of the transport stream in RTP, UDP, and IP packets. The MTS-E core can be programmed to perform RTP encapsulation, while the companion UDPIP core from CAST supports UDP/IP encapsulation.
The core is easy to integrate in systems with or without a host processor. Once configured via its control registers, the MTS-E operates on a standalone basis. Input streams and TS/RTP packet output are sent via dedicated AXI4-Streaming interfaces, enabling direct connection to hardware media encoders and hardware stacks for UDP or TCP. Status and control registers are accessible by an AXI4-Lite interface.
The MTS-E core is available in RTL source or as a targeted FPGA netlist. Subsystems integrating the core with H.264 encoder, UDP/IP, and eMAC cores are also available from CAST, and can enable rapid video over IP systems development.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
The versatile MTS-E core is especially suitable for video conferencing systems, surveillance systems, and other multi-channel media streaming applications and devices featuring media streaming over IP networks.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts and comprehensive user documentation.