Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

MPEG Transport Stream Multiplexing & Encapsulation

  • Compliant to ISO/IEC 13818-1
  • Two input stream channels (additional channels upon request)
  • Supports common stream types
    • Audio
    • Video
    • Metadata
  • Flexible Encapsulation
    • Programmable Packetized Elementary Stream (PES) packet size
    • Programmable TS packet group size
    • Optional Program Info support
    • Optional Elementary Stream Info support

RTP Encapsulation

  • Software enabled/disabled encapsulation of the MPEG Transport stream in RTP packets

Easy Integration

  • Standalone, processor-less operation
  • AMBA® AXI Interfaces
  • AXI4-Lite™ Control/Status register interfaces
  • AXI4-Streaming™ interfaces for packet data
  • Optional Avalon® SoC bus interface
  • Configurable input and output buffers sizes
  • The MTS-E can be delivered pre-integrated with:
    • Video Encoder cores from CAST
    • UDP/IP Hardware Stack from CAST, and eMAC core from Altera, Xilinx, or other third-party

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

  • H2642RTP Hardware RTP Stack for H.264
  • H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem
  • UDPIP UDP/IP Hardware Protocol Stack Core

MTS-E MPEG Transport Stream Multiplexing & Encapsulation Engine

The MTS-E core multiplexes and encapsulates audio, video and metadata streams in a single MPEG Transport Stream (TS), and optionally encapsulates the TS packets in Real-Time Transport Protocol (RTP) packets.

Under its default configuration, the MTS-E multiplexing and encapsulation engine supports two input stream channels, e.g., one Audio and one Video. Configurations with more than two input stream channels can be made available upon request.

The output transport stream can be forwarded for local storage or transmitted over an Internet Protocol (IP) or other network. Streaming over IP networks often imposes further encapsulation of the transport stream in RTP, UDP, and IP packets. The MTS-E core can be programmed to perform RTP encapsulation, while the companion UDPIP core from CAST supports UDP/IP encapsulation.

The core is easy to integrate in systems with or without a host processor. Once configured via its control registers, the MTS-E operates on a standalone basis.  Input streams and TS/RTP packet output are sent via dedicated AXI4-Streaming interfaces, enabling direct connection to hardware media encoders and hardware stacks for UDP or TCP. Status and control registers are accessible by an AXI4-Lite interface.

The MTS-E core is available in RTL source or as a targeted FPGA netlist. Subsystems integrating the core with H.264 encoder, UDP/IP, and eMAC cores are also available from CAST, and can enable rapid video over IP systems development.

See representative implementation results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Applications

The versatile MTS-E core is especially suitable for video conferencing systems, surveillance systems, and other multi-channel media streaming applications and devices featuring media streaming over IP networks.

Block Diagram

mts-e block diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts and comprehensive user documentation.

 

tw    fbk    li    li    li
Top of Page