Xilinx results for a 32-bit version configuration of the core with a transmit FIFO=512B and a receive FIFO=512B, optimized for speed, with IOBs assuming all core I/O is routed off-chip.
| Xilinx Devices | Slices | BRAM |
IOB | Fmax (MHz) |
ISE Version |
| Spartan-3E 3S1200E-5 |
5375 | 4 | 238 | 65 | 12.2i |
| Spartan-6 6SLX75-3 |
1735 | 3 | 238 | 80 | 12.2i |
| Virtex-6 6VLX75T-3 |
694 | 3 | 238 | 160 | 12.2i |