The following are sample Altera results optimized for speed for a typical 32-bit implementation, and implemented with TDRAM, RDRAM and ARAM (2x512*32-bit, 64*16-bit). The performance reported is for the host side clock (clkdma).
| Altera Devices | IOBs | Utilization | Performance Fmax |
|
| Les/ALUTs | Memory | |||
| Cyclone EP1C20-6 |
258 | 3950 | 9 M4Ks | 97 MHz |
| Cyclone-II EP2C15-6 |
258 | 3858 | 9 M4Ks | 100 MHz |
| Cyclone-III EP3C16-6 |
258 | 3841 | 3 M9Ks | 110 MHz |
| Stratix EP1S10-5 |
258 | 3950 | 9 M4Ks | 106 MHz |
| Stratix-II EP2S15-3 |
258 | 2296 | 3 M9Ks | 146 MHz |
| Stratix-III EP3SL50-2 |
258 | 2598 | 3 M9Ks | 189 MHz |