- Network interface features
- Supports 10/100Mb/s data transfer rates
- Media Independent Interface (MII)
- Optional Reduced Media Independent Interface (RMII)
- Data link layer functionality
- Meets the IEEE 802.3 CSMA/CD standard
- Full or half duplex operation
- Flexible address filtering
- External RAM for storing MAC addresses
- Up to 16 physical addresses
- 512 bit hash table for multicast addresses
- Control and status registers
- Configurable 8/16/32 bit data bus length
- Single interrupt line
- Interrupt mitigation control mechanism
- DMA Controller
- Configurable 8/16/32 bit data bus length
- Configurable address bus length
- Big or little endian data byte ordering
- Scatter/gather capabilities
- Programmable burst length
- Intelligent arbitration between transmit and receive processes
- Descriptor/buffer architecture for data storage
- Descriptor "ring" or "chain" structures
- Automatic descriptor list pooling
- Transmit/Receive dual port RAM interfaces
- Operates as internal configurable FIFOs
- Programmable threshold levels
- "Store and forward" functionality
- Optional standard bus interfaces include AMBA, OCP, and OPB
- Optional Linux driver
Call or click.
Options for this Core
- MAC-L 10/100 Ethernet MediaAccess Controller Lite
- MAC-1G 1-Gigabit Ethernet Media Access Controller
- MAC-1G-L Lite 1-Gigabit Ethernet Media Access Controller
- MAC-1G-PCS Gigabit Ethernet MAC Controller Physical Coding Sublayer
- MAC-PCI Ethernet MAC Controller with PCI Host Interface
Ethernet MAC IP Core MAC 10/100 Ethernet Media Access Controller Core
Implements a high-speed (10/100 Mbps), half- and full-duplex LAN controller using the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by IEEE 802.3 for media access control over the Ethernet.
For broad compatibility and easy integration, the core works with any MII-compliant external PHY transceiver. (SMII & RMII support is available.)
The core has a generic host-side interface designed for easy compatibility with a variety of external CPUs or standard bus controllers such as PCI. This host interface can be configured to work with 8-, 16- or 32-bit data bus lengths with big or little endian byte ordering, and is compatible with most modern virtual component interfaces. Optional standard interfaces such as AMBA, OCP, and OPB are available.
The MAC was developed for reuse in ASIC and FPGA implementations and has been implemented in several commercial products. The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset.
See representative implementation results (each in a new pop-up window):
The MAC core can be utilized for a variety of interface applications including network Interface Cards (NICs); routers and switching hubs; and many Systems On Chip (SoC) applications.
Pre-Integrated IP Platform
The R8051MAC Controller combines the MAC with an 8051-compatible core and is useful for quickly implementing Ethernet devices in many applications. The 8051 operates as a system host, communicating with the MAC through shared RAM memory and by direct interface to its Control and Status Registers (CSRs). The complete platform consists of the R8051MAC core together with the following components:
- Dual port RAMs for transmit FIFO, receive FIFO and address filtering RAM.
- External PHY transceiver for connection with Ethernet network.
- Shared RAM, which stores data buffers and descriptor list.
The FIFO memories can be resized according to Ethernet network requirements. External host interfaces can be customized for use in 8-, 16- or 32-bit systems. Contact CAST for any required modifications.
The following parameters allow adjusting the MAC to the requirements of the target application or technology:
- CSR data bus width – 8 or 16 or 32
- data interface bus width – 8 or 16 or 32
- data interface address bus width – 8 to 32
- transmit FIFO size – 64B to 64kB
- receive FIFO size – 64B to 64kB
Following optional modules may be ordered according to the user’s application:
- RMII - Reduced MII interface instead of standard MII
- SMII - Serial MII interface instead of standard MII
- FC – Flow Control
- SC - Statistical Counters Controller
- FCSTAT – Flow Control Statistics
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive simulation and rigorous code coverage measurements. The megafunction was also prototyped in FPGA.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench including the core and:
- On chip dual port RAMs
- Bus/behavioral models of host, shared RAM and PHY devices
- Clock generator
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide