The following implementation numbers were optimized for area with the PCI clock constrained to 33 MHz and the MAC clock constrained to 25 MHz.
| ASIC Technology |
Cell Area | NAND2 Area |
Approx. Area |
| TSMC 0.09µ | 82,062 | 2.8224 | 29,075 gates |
| TSMC 0.13µ |
151,607 | 5.0922 |
29,772 gates |
| TSMC 0.18µ | 280,249 | 9.9792 | 28,083 gates |