Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

Processor Peripherals
AHB 32-bit DMA
AMBA Infrastructure Cores

Legacy Processors
See Legacy Cores >

These video and image compression cores help you handle video compression for demanding, high-quality applications or choose the best type of image compression for your specific system.

JPEG 2000
Encoder
J2K Platform

Block/Raster Converters
block-to-raster
raster-to-block
raster-block bidirect

Lossless Compression
LJPEG Encoder
LJPEG Decoder
JPEG-LS Encoder

Functions & Converters
Color Space Converter

Video Deinterlacers
Basic

Quickly complete the standrd parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores. Choose high-speed DisplayPort or PCI Express, Ethernet MACs, the CAN bus for automotive systems, and more.

High-Speed Serial
PCI Express
Family Overview
x1/x4
x8
application interface

Parallel
ECP slave
ATA/IDE interface

PCI — Target
32-bit
32-bit multi
64-bit
PCI — Master
32-bit
32-bit multi
64-bit
PCI — Host Bridge
32 bit
32 bit - AHB
32 bit & device - AHB

TCP/IP Stacks
UDP/IP stack

Ethernet MAC
Device Controllers

10/100
10/100 lite
Gigabit
Gigabit lite
Gigabit PCS

MAC Platforms
MAC/PCI

Customers find these cores to be an excellent solution for preserving existing product board designs when critical chips are no longer available for purchase.

 
80186XL
80186EC
80188EC
80251
387L math

DSPs
32025 16-bit
32025TX 16-bit

 

 

Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Cores for integrating security, controlling devices and displays, and other SoC functions.

Device Controllers
smart card reader

IR Remote Controls
RC5
NEC

Audio Interfaces
I2S-SC
I2S-MC
SPDIF

  • Network Interface Features
    • Support for 10/100 Mbps data transfer rate
    • Media Independent Interface (MII) for 10/100 Mbps operation
    • Automated MII Management interface
  • Data Link Layer Functionality
    • Support for the IEEE 802.3 CSMA/CD standard
    • Full or half duplex operation
    • Flexible address filtering
    • External RAM for storing MAC addresses
    • Up to 16 physical addresses
    • 512 bit hash table for multicast addresses
  • PCI Local Bus Interface Support
    • PCI spec 2.3 compliant
    • 33 MHz performance
    • 32-bit data path
    • Zero wait states burst mode
    • Full bus master/target functionality
    • Single interrupt
    • Type 0 Configuration Space
    • Support for backend initiated target retry, disconnect and abort
  • DMA Controller
    • Scatter/gather capabilities
    • Programmable burst length
    • Intelligent arbitration between transmit and receive processes
  • Descriptor / Buffer Architecture for Data Storage
    • Descriptor "ring" or "chain" structures
    • Single descriptor can point to two data buffers
    • Auto descriptor list pooling
  • Low Power Capabilities
    • Independent clocks for data and control paths
    • Running/Suspended/Stopped modes of operation
    • Clock switching support
  • Transmit/Receive Dual Port RAM Interfaces
    • Operating as internal configurable FIFO’s
    • Programmable threshold levels
    • "Store and forward" functionality
  • Dedicated Linux Driver

Contact Sales
Call or click.
+1 800.391.8300

PDF Datasheets

ASIC
Altera, Xilinx

Related Products

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  • MAC-1G-L Lite 1-Gigabit Ethernet Media Access Controller
  • MAC-1G-PCS Gigabit Ethernet MAC Controller Physical Coding Sublayer
  • PCI-T32 32-bit, 33 MHz PCI Target Interface
  • PCI-T32MF 32-bit, 33 MHz Multifunction Target Interface
  • PCI-T64 64-bit, 66 MHz PCI Target Interface
  • PCI-M32 32-bit, 33 MHz PCI Master/Target Interface
  • PCI-M32MF Multi-Function PCI Master/Target Interface
  • PCI-M64 64-bit, 66 MHz PCI Master/Target Interface
  • PCI-HB 32-bit/33,66Mhz PCI Host Bridge
  • PCI-DHB-AHB PCI - AMBA AHB Device/Host Bridge Core
  • PCI-HB-AHB PCI to AMBA AHB Host Bridge Core

IP Subsystem MAC-PCI Ethernet MAC Controller with PCI Host Interface Core

The MAC-PCI IP core is a combination of the Ethernet Media Access Controller (MAC) HDL core - and the 32-bit 33 MHz Master/Slave PCI Host Interface core (PCI-M32). The core is intended to simplify the Ethernet networking support development in PCI based systems and applications.

A variety of available PHY interfaces facilitates the controller’s integration with a wide range of third-party transceivers. While the implementation of the most common PCI Local Bus interface guarantees seamless integration with a large number of PCI-equipped hardware devices, an available Linux driver allows users to skip basic software development stages and concentrate on designing the main application. Both the integrated scatter/gather DMA Controller and extended filtering features decrease CPU overhead, whereas advanced interrupt mitigation lowers the number of necessary interrupt support routines. Configurable internal FIFO’s architecture and low power capabilities make MAC-PCI a perfect solution for both resource and power limited applications.

The MAC-PCI is a design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states, and a synchronous reset; therefore, scan insertion is straightforward.

See representative implementation results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Applications

Block Diagram

mac-pci-block-diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive functional and post‑route simulation, and has achieved high Code Coverage. An FPGA prototype was used to verify the functionality in a Linux OS-based environment.

Deliverables

The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation:

 

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