IP Subsystem MAC-PCI Ethernet MAC Controller with PCI Host Interface Core

The MAC-PCI IP core is a combination of the Ethernet Media Access Controller (MAC) HDL core - and the 32-bit 33 MHz Master/Slave PCI Host Interface core (PCI-M32). The core is intended to simplify the Ethernet networking support development in PCI based systems and applications.

A variety of available PHY interfaces facilitates the controller’s integration with a wide range of third-party transceivers. While the implementation of the most common PCI Local Bus interface guarantees seamless integration with a large number of PCI-equipped hardware devices, an available Linux driver allows users to skip basic software development stages and concentrate on designing the main application. Both the integrated scatter/gather DMA Controller and extended filtering features decrease CPU overhead, whereas advanced interrupt mitigation lowers the number of necessary interrupt support routines. Configurable internal FIFO’s architecture and low power capabilities make MAC-PCI a perfect solution for both resource and power limited applications.

The MAC-PCI is a design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states, and a synchronous reset; therefore, scan insertion is straightforward.

See representative implementation results (each in a new pop-up window):

Applications

• PCI-based systems
• Network Interface Controllers

Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive functional and post‑route simulation, and has achieved high Code Coverage. An FPGA prototype was used to verify the functionality in a Linux OS-based environment.

Deliverables

The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation:

• Verilog or VHDL RTL source code (EDIF netlist available)
• Synthesis script (ASICs) or place and route script (FPGAs)
• Simulation support
• Sophisticated self-checking HDL Testbench including everything needed to test the core (Verilog versions use Verilog 2001)
• Comprehensive documentation

This core is sourced from the IP experts at Evatronix SA.