Results below are optimized for speed for a typical 32-bit data bus configuration with a 16-bit address bus, transmit & receive FIFOs with a depth of 9 bits. I/Os assume all core I/O is routed off-chip.
| Xilinx Device |
Slices | BRAM | I/Os | Fmax (MHz) |
ISE Version |
| Spartan-3E 3S1200E-5 |
1086 | 3 | 242 | 100 | 10.1.02 |
| Virtex-4 4VLX15-12 |
1038 | 3 | 242 | 147 | 10.1.02 |
| Virtex-5 5VLX30-3 |
507 | 3 | 242 | 202 | 10.1.02 |