- Network interface features
- Supports 10/100Mb/s data transfer rates
- Media Independent Interface (MII)
- Optional Reduced Media Independent Interface (RMII)
- Optional Serial MII interface instead of standard (SMII)
- Data link layer functionality
- Meets the IEEE 802.3 CSMA/CD standard
- Full or half duplex operation
- Flexible address filtering
- External RAM for storing MAC-L addresses
- Up to 16 physical addresses
- 512 bit hash table for multicast addresses
- External CAM interface
- Transmit/Receive dual port RAM interfaces
- Operates as internal configurable FIFOs
- Programmable threshold levels
- "Store and forward" functionality
Call or click.
- MAC 10/100 Ethernet Media Access Controller, the basic controller in the family. It operates at 10/100 Mbps speed and contains an integrated descriptor based DMA.
- MAC-1G 1-Gigabit Ethernet Media Access Controller, the most feature-rich controller in the family. Operates at 10/100/1000 Mbps speed modes, and contains an integrated descriptor based DMA. Its features include: MII/GMII PHY management, Flow Control, and a full set of Statistical Counters.
- MAC-1G-L Lite 1-Gigabit Ethernet Media Access Controller, optimized for size. It shares the speed of the MAC-1G but with reduced complexity. It communicates with the host using a direct FIFO interface.
- MAC-1G-PCS Gigabit Ethernet MAC Controller Physical Coding Sublayer.
- MAC-PCI Ethernet MAC Controller with PCI Host Interface.
- R8051XC-MAC-L-HA, an Ethernet controller integrated with the R8051XC Microcontroller core and enriched by a TCP/IP hardware accelerator.
Ethernet MAC IP Core MAC-L 10/100 Ethernet MediaAccess Controller Lite Core
The MAC-L Ethernet controller is a synthesizable HDL core of a high-speed LAN controller. It implements Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by IEEE 802.3 for media access control over the Ethernet.
For broad compatibility and easy integration, the core works with any MII-compliant external PHY transceiver (SMII & RMII support is available.)
The core has an interface for external dual port RAMs serving as configurable FIFO memories with separate memories for transmit and receive processes. Using the FIFOs additionally isolates the MAC from the external host and provides resolution in case of latency of the external bus.
From the host side the MAC-L uses a generic interface with independent transmit and receive paths. The flexible design allows for using the MAC-L in various applications, especially switching and low gate-count applications.
The MAC-L was developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset.
See representative implementation results (each in a new pop-up window):
- Very low gate count per instance makes the IP core an excellent choice for multiport Ethernet devices
- High configurability level makes the controller suitable for a large scope of SoC applications
- Variety of available physical layer interfaces - MII, SMII, RMII gives excellent support for different market solutions
The MAC-L core can be utilized for a variety of applications including:
- Routers and Switching hubs
- Low gate count applications
- Network Interface Cards (NIC)
- Systems On Chip (SoCs) applications
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core functionality was verified in a FPGA prototype working in an Ethernet 10/100 Mbit network.
The MAC-L is used to implement 10 and 100 Mbit/s Ethernet networks interface in a system. The example application system consists of the microcontroller (MCU) and the MAC-L module. The host transmits and receives frames through the FIFO memories interfaces (transmit and receive RAMs). The operation mode of the MAC-L is provided via set of configuration pins that can be mapped into microcontroller memory/port(s) or hard-coded to the one desired configuration.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, the core with memories, bus/behavioral models of host and PHY devices, and clock and reset generators
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide