Xilinx results for a 32-bit version configuration of the core with a transmit FIFO=512B and a receive FIFO=512B, optimized for speed, with IOBs assuming all core I/O is routed off-chip.
| Xilinx Devices |
Slices |
BRAM |
IOB |
Fmax Host Side |
ISE Version |
| Virtex-4 4VFX20-12 |
5844 | 5 | 246 | 106 MHz | 9.2.02i |
| Virtex-5 5VLX30-3 |
3011 | 3 | 246 | 136 MHz | 9.2.02i |
| Virtex-6 6VLX75T-3 |
1683 | 3 | 246 | 200 MHz | 12.2i |
| Spartan-6 6SLX25-3 |
1849 | 3 | 246 | 95 MHz | 11.5 |