- IEEE 802.3-2002 Standard compliance
- Configurable and monitorable through the Management Interface
- 1000BASE-X Auto-Negotiation process support for information data exchange with a link partner
8B-10B Data Encoder/Decoder - Synchronization Module
- MAC frames encapsulation/de-encapsulation
- Data transmitting/receiving
- Carrier-extension transmitting/receiving
- Idle ordered sets for transmitting/receiving
- Full and half duplex mode support
- Standard Register Set
- PHY loopback mode support with MGM write control register command
Benefits
- Possibility for FPGA implementation with 8B-10B Data Encoder/Decoder located in built-in memory blocks
- Perfect for integrating an Ethernet MAC controller with an optical transceiver through Physical Medium Attachment (PMA) sublayer
Ethernet MAC IP Core MAC-1G-PCS Gigabit Ethernet MAC Controller Physical Coding Sublayer Core
The MAC-1G PCS is an IP core of a 1 Gigabit Physical Coding Sublayer (PCS) that meets all IEEE 802.3-2002 Standard requirements. The MAC-1G PCS provides both PCS interfaces, GMII and PMA. It also features the Management Interface (MGM) for communication with the Station Management (STA).
The MAC-1G PCS has been developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore, scan insertion is straightforward.
See representative implementation results (each in a new pop-up window):
Block Diagram
Example Application
The following figure presents typical application of the MAC-1G PCS IP core.
The MAC-1G PCS provides a sublayer needed for establishing Gigabit Ethernet communication over fiber-optic cable. The common use of such an optical connection is implementing TCP/IP stack for connecting embedded systems with the computer network.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
- Sophisticated self-checking HDL Testbench
- Simulation scripts, vectors, expected results, and comparison utility
- Synthesis (soft) or place and route (firm) script
- Comprehensive user documentation, including detailed specifications and a system integration guide
This core is sourced from the IP experts at Evatronix SA.
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