Low-Latency Ethernet MAC
- Supports IEEE 802.3
- Enables high-precision syn-chronization in TSN networks
- Egress latency:
- Tx clock cycles
- Ingress latency: 6 Rx clock cycles
- Full duplex point-to-point links
Easy System Integration
- Autonomous operation, re-quires no host assistance once programmed
- Host Interfaces
- Avalon-MM: memory mapped
- Avalon-ST: stream
- PHY Interfaces
- Media Independent Interface (MII) for 10/100Mbps
- Gigabit Media Independent Interface (GMII) for 1Gbps
- Reduced Gigabit Media Inde-pendent Interface (RGMII) for 10/100/1000 Mbps
- MDIO interface for PHY con-figuration and management
- Certified ISO-26262 “ASIL-D Ready”
- Spatial redundancy for inner logic protection
- Clock activity monitoring
- Source code VHDL or Verilog RTL or targeted netlist
- Sample synthesis and simula-tion scripts
- Comprehensive documentation
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- EMAC-1G 10/100/1000 Ethernet MAC with DMAs
Latest White Paper
This white paper provides an introduction to Time-Sensitive Networking (TSN), an evolving set of IEEE standards that enable the transmission of real-time video and other time-sensitive data over Ethernet. TSN provides for low-latency transmission, time scheduling, and resource sharing, and is increasingly used for automotive buses and other demanding networking applications.
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LLEMAC-1G Low-Latency 10/100/1000 Ethernet MAC
The LLEMAC-1G implements an Ethernet Media Access Controller (MAC) compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications. Featuring extremely low egress and ingress latency, the core is ideal for the implementation of TSN Ethernet nodes, live streaming and other devices requiring minimum latency in the reception and transition of Ethernet frames.
The core supports full-duplex operation, supports jumbo frames, provides statistics counters, and it is easy to integrate and implement. The LLEMAC-1G exchanges data with the host system via a byte-wide streaming interfaces, and connects to the external PHY via an MII, GMII or RGMII interfaces. An independently clocked, 32-bit wide memory mapped interface provides access to the cores control and status registers. The default core interfaces comply to the Avalon standard, but AMBA™ AHB or AXI can also be made available upon request.
The LLEMAC-1G is available in two versions: Normal, and Safety-Enhanced.
The Safety-Enhanced version implements clock activity monitors and uses spatial redundancy for protecting the inner logic of the core. The deliverables for this version include a Safety Manual (SAM);, a Failure Modes, Effects and Diagnostics Analysis (FMEDA);, and the ISO-26262 “ASIL-D Ready” cer-tificate, issued by SGS-TÜV Saar GmbH.
The core is provided in Verilog RTL or as targeted FPGA netlist, and its deliverables include everything required for a success-ful implementation, including an extensive testbench, sample scripts and comprehensive documentation.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (in a new pop-up window):
The core's deliverables include everything required for a successful implementation, including an extensive testbench, sample scripts and comprehensive documentation.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.