LIN Core —XILINX FPGA Results

The LIN can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample Xilinx performance and resource utilization data assuming all I/Os are routed off-chip. Please contact CAST to get characterization data for your target configuration and technology.

Family
Device LUTs Fmax (MHz)2
Master Slave1
Spartan-7
xc7s50-2 333 581 197
Artix-7
xc7a15t-3 341 597 222
Kintex-7
xc7k160t-3 348 601 263
Virtex-7
xc7vx485t-3 349 597 333
Kintex-Ultrascale
xcku035-3-e 333 595 357
Virtex- Ultrascale
xcvu080-3-e 355 607 454
Kintex-Ultrascale+
xcku13p-3-e 359 611 526
Virtex- Ultrascale+
xcvu13p-3-e 355 606 588

Notes:
1) Slave implemented with clock synchronization
2) Working frequency of LIN controller is 4 MHz

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