CAST LIN Core —XILINX FPGA Results

Results are for a Slave implemented with clock synchronization.

Supported
Family
Slices
master/slave
(optimized for area)
IOBs
(assuming all core I/Os and clocks are routed off-chip)
BRAM Fmax
master/save
(MHz)
(working frequency of LIN controller is 4 MHz)
ISE Version
Spartan-3E
3S1200E-5
325 / 521 28 0 82 / 78 12.2
Spartan-6
6SLX25-3
115 / 209 28 0 139 / 124 12.2
Virtex-4
4VLX15-11
337 / 553 28 0 169 / 141  
Virtex-5
5VLX30-3
120 / 181 28 0 172 / 199 12.2
Virtex-6
6VLX130T-3
89 / 201 28 0 236 / 212 12.2

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