Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
Automotive Ethernet
TSN Ethernet Subsystem
CAN-to-TSN Gateway
LIN
LIN Bus Master/Slave
LIN Bus VIP
SENT/SAE J2716
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

  • Supports ISO 17987 Part 1-7
    • Backwards compatible
  • Master and Slave node BFMs
  • Node configuration and identification services
  • Automatic frame segmentation and re-assembly of network layer messages (FF, CF)
  • Automatic frame scheduling to time slot/time base including collision resolution
  • Frame transmission ordering and endianness
  • Status management that provides error handling and error signaling
  • Wake and Go-to-Sleep modes
  • Diagnostics
  • Response pending
  • Diagnostic and Interleaved Diagnostic mode
  • Verified with CAST LIN IP 

Additional Features

  • Timing class models all timing parameters (randomize, modifiable)
  • Transport and Network layer timing parameter including time base and jitter
  • Multiple bit rates from 1Kbps to 20Kbps
  • Inter-frame delay
  • Error detection (callback, bit stuffing) and injection
  • Random configuration
  • Node type, bit timing rate, time base, jitter
  • Error injection/Callbacks
  • Functional Coverage
  • Protocol checking
  • Protocol analyzer log
  • Compliance testsuite (17987 Part 6)

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

  • LIN Bus Master/Slave Controller Core
  • CSENT SENT/SAE J2716 Controller Core
  • CAN-CTRL CAN 2.0 & CAN FD Bus Controller Core

Articles

EDN Asia: LIN Bus – A Cost-Effective Alternative to CAN

EET Asia: LIN Bus – An Emerging Standard for Body Control Applications

TI: LIN protocol overview

National Instruments: Introduction to LIN protocol

LIN-VIP LIN Verification IP

LIN-VIP is a comprehensive VIP package for LIN controllers. SoC and IP designers use this LIN-VIP package to ensure complete verification of their designs and full protocol and timing compliance.LIN is part of the Automobile IP cores line from CAST, Inc.

LIN-VIP implements a ready-to-use set of models, protocol checkers, and compliance testsuites in 100% native SystemVerilog and UVM. It supports the latest relevant specifications, including LIN ISO 17987 Part 1-7.

The system configuration uses an LDF class describes complete cluster configuration and information mapping

Block Diagram

Support

The LIN-VIP as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The LIN-VIP includes everything required for successful implementation:

 

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