LIN Core — Lattice Implementation Results

The LIN core can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following are sample implementation data for the core assuming all I/Os are routed off-chip. Please contact CAST to get characterization data for your target configuration and technology.

Family

Device Config

Logic

Fmax2

(MHz)
MachXO2
7000HC-5
Master
269 Slices
536 LUT4s
68
MachXO2
7000HC-5
Slave1
419 Slices
836 LUT4s
55

Notes:
1) Slave implemented with clock synchronization
2) Working frequency of LIN controller is 4 MHz

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