- Support of LIN specification 2.0, 2.1, and 2.2A
- Backwards compatible with LIN specification 1.3
- Configurable for support of master or slave functionality
- Programmable data rate between 1 Kbit/s and 20 Kbit/s (for master)
- Automatic bit rate detection (for slave)
- 8-byte data buffer
- 8-bit host controller interface
- Wrappers for 32bit busses (e.g. APB) can be made available upon request
- Slave can be implemented with or without clock synchronization
- Fully synchronous design, available in VHDL or Verilog, completely synthesizable
- The LIN Controller synthesizes to approximate 2500 to 3800 gates depending on the configuration
- Robustly verified and multiple times production proven IP core
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- 11/10/15, Avery, CAST, and Rianta Roll Together on Automotive Ethernet and CAN FD IP and VIP Solutions
National Instruments: Introduction to LIN protocol
LIN LIN Bus Master/Slave Controller Core
The LIN core is a communication controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol Specification. The LIN controller can be implemented as a master or as a slave and operate on LIN 1.3, 2.0, 2.1 or 2.2 LIN network. It uses a single master/multiple slave concept for message transfer between nodes of the LIN network. The message transfer can be controlled via a micro controller interface and a LIN transceiver is needed for the connection to the LIN bus.
The LIN core is a microcode-free design developed for reuse in ASIC and FPGA im-plementations. The scan-ready design is strictly synchronous with positive-edge clocking and no internal tri-states. The robustly verified core has been production proven multiple times.
See representative implementation results (each in a new pop-up window):
The LIN core can be utilized for a variety of applications including;
- low cost automotive networks
- interfaces for sensors and actuators
The LIN core can be modified to include an acceptance filter. With that, a simple LIN slave that transmits response frames for only one identifier could be realized without the assistance of a host controller.
Please contact CAST, Inc. directly for any required modifications.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been verified through extensive simulation and rigorous code coverage measurements.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sample driver in C code
- Simulation script, vectors, expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide