The I2C bus uses two wires to transfer information between devices connected to the bus: SCL (serial clock line) and SDA (serial data line).
- Master Transmitter Mode — Serial data output through SDA while SCL outputs the serial clock.
- Master Receiver Mode — Serial data is received via SDA while SCL outputs the serial clock.
- Slave Receiver Mode — Serial data and the serial clock are received through SDA and SCL.
- Slave Transmitter Mode — Serial data is transmitted via SDA while the serial clock is input through SCL.
- Data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode.
- Bi-directional data transfer.
- Own address and General Call address detection.
- 7-bit addressing format.
- Fixed data width of 8 bits.
- Data transfer in multiples of bytes.
- One-byte write and read buffer.
I2C IP Core I2C Philips Serial Bus Interface Core
I2C Bus Controller logic provides a serial interface that meets the Philips I2C bus specification and supports all transfer modes from and to the I2C bus.
The I2C logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register (i2csta) reflects the status of I2C Bus Controller and the I2C bus.
The I2C is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward.
See representative implementation results (each in a new pop-up window):
Benefits
- I2C provides a convenient interface to I2C bus – the de facto world standard in a broad range of applications
- I2C uses only 2 wires to connect to virtually an unlimited number of devices, therefore minimizing interconnections and usage of IC pins in the user application
- I2C standard implements a simple and efficient bus which does not require additional logic such as address decoders or arbiters
Applications
The I2C can be utilized for a variety of bus applications including:
- Embedded microcontroller systems
- Communication systems
Block Diagram
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive synthesis, place and route and simulation runs. It has also been em-bedded in several products, and is proven in both ASIC and FPGA technologies.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Testbench
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide
This core is sourced from the IP experts at Evatronix SA.
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