Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Standards Compliance

  • Phillips I2C
  • SMBus Version 2.0 & 3.0

Operation Modes

  • Master Transmitter Mode
  • Master Receiver Mode
  • Slave Receiver Mode
  • Slave Transmitter Mode

Functionality

  • Seven-bit Addressing
  • Byte-wide Transfers
  • Bus Arbitration
  • Clock signal (SCL) generation (in master mode) and data synchronization
  • START/STOP Timing detection and generation
  • Timeout/Bus error detection
  • Clock-Low Extension to allow fast-master slow-slave communication
  • Configurable glitches filter for clock and data serial lines
  • Bus status reporting

Interfaces

  • I2C–SMBUS
    • A pair of unidirectional signals for SCL and SDA
    • Control for the serial line buffers/drivers
  • Host
    • 32-bit APB or 8-bit generic (8051-like) for register access
    • Interrupt line
  • Clocks
    • Core operates on the host-interface clock
    • Reference clock signals used to generate the serial clock (SCL)

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

  • I2C-VIP I2C Bus Verification IP
  • I2C-M I2C Bus Master Controller Core
  • I2C-S I2C Bus Slave Controller Core

News Releases

Additional Information

I2C-SMBUSI2C & SMBus Controller Core

The I2C-SMBUS core implements a serial interface controller for the Inter-Integrated Circuit (I2C) bus and the latest specification of the System Management Bus (SMBus).

i2c-smbus bus controller ip core block diagram

The core can be programmed to operate either as a bus master or a slave, and it is easy to program and integrate. An arbitration mechanism allows operation in a multiple master bus and the SMBus provisioned clock synchronization mechanism allows fast-master/slow-slave communication. Furthermore, the core detects timeout and errors to prevent bus deadlocks, and can filter out glitches on the serial line. The control, status, and data registers of the I2C-SMBUS core are accessible via an AMBA APB or a generic memory mapped interface.

The I2C-SMBUS is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design uses rising-edge-triggered flip-flops only with the reset type (i.e. asynchronous and/or synchronous) being configurable at synthesis time. VIP from Boost Valley for easy I2C verificationFurthermore, the core does not use tri-states; therefore scan insertion is straightforward.

I2C verification IP (VIP) is available for this I2C bus controller core.

Implementation Results

I2C-SMBUS core reference designs have been evaluated in a variety of technologies.

See representative implementation results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Applications

The I2C-SMBUS can manage the communication of a host processor with peripherals such as sensors, smart battery subsystems, analog front ends, analog-to-digital and digital to analog converters, and display controllers.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

 

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