- Phillips I2C
- SMBus Version 2.0 & 3.0
- PMBus Version 1.3 or earlier
- Master Transmitter Mode
- Master Receiver Mode
- Slave Receiver Mode
- Slave Transmitter Mode
- Seven-bit Addressing
- Byte-wide Transfers
- Bus Arbitration
- Clock signal (SCL) generation (in master mode) and data synchronization
- START/STOP Timing detection and generation
- Timeout/Bus error detection
- Clock-Low Extension to allow fast-master slow-slave communication
- Configurable glitches filter for clock and data serial lines
- Bus status reporting
- A pair of unidirectional signals for SCL and SDA
- Control for the serial line buffers/drivers
- 32-bit APB or 8-bit generic (8051-like) for register access
- Interrupt line
- Core operates on the host-interface clock
- Reference clock signals used to generate the serial clock (SCL)
Call or click.
- SPMI-CTRL MIPI SPMI Master or Slave Controller
- I2C-VIP I2C Bus Verification IP
- I2C-M I2C Bus Master Controller Core
- I2C-S I2C Bus Slave Controller Core
I2C-SMBUSI2C & SMBus Controller Core
The I2C-SMBUS core implements a serial interface controller for the Inter-Integrated Circuit (I2C) bus and the System Management Bus (SMBus). The core is also suitable for implementing controllers for the Power Management Bus (PMBUS).
The core can be programmed to operate either as a bus master or a slave, and it is easy to program and integrate. An arbitration mechanism allows operation in a multiple master bus and the SMBus provisioned clock synchronization mechanism allows fast-master/slow-slave communication. Furthermore, the core detects timeout and errors to prevent bus deadlocks, and can filter out glitches on the serial line. The control, status, and data registers of the I2C-SMBUS core are accessible via an AMBA APB or a generic memory mapped interface.
The I2C-SMBUS is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design uses rising-edge-triggered flip-flops only with the reset type (i.e. asynchronous and/or synchronous) being configurable at synthesis time. Furthermore, the core does not use tri-states; therefore scan insertion is straightforward.
I2C verification IP (VIP) is available for this I2C bus controller core.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
The I2C-SMBUS can manage the communication of a host processor with peripherals such as sensors, smart battery subsystems, analog front ends, analog-to-digital and digital to analog converters, and display controllers.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
- RTL source code or targeted FPGA netlist
- Sample simulation and synthesis script
- Extensive documentation
- Sample SMBus software driver