Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

  • Supports latest specification: Philips/NXP Standard Version 1 through Version 6 (April 2014)
  • Delivered pre-configured and set up for immediate use with the
  • I2C-SMBUS Controller Core
  • Language: System Verilog
  • Methodology Support:
  • UVM v1.1d
  • Simulators supported:
    • Mentor Questa® Advanced Simulator
    • Synopsys VCS®

I2C Verification Features

  • Multiple Agents:
    supports both multi-master and multi-slave configurations
  • Addressing:
    7-bit address
  • General Call support
  • Standard Mode support
  • Read Request support
  • Multi-byte read/write support
  • Slave Response Control:
    Implements user control of slave response fields such as data, slave busy, slave sending NACK, etc.

VIP Configurations

  • I2C Timing Parameters
  • I2C Master/Slave Address

Contact Sales
Call or click.
+1 201.391.8300

PDF Datasheets

ASIC

Related Products

News Releases

I2C-VIPI2C Bus Master/Slave Verification IP

The I2C-VIP verification IP package makes verification of an I2C bus controller easier and more complete, and it comes ready for immediate use with the I2C Bus Controller IP core from CAST.

i2c-m block diagram

The I2C-VIP supports the latest iteration of the Inter-Integrated Circuit standard—NXP Version 6 (April 2014)—and the popular UVM verification methodology.

The I2C-VIP is highly flexible and broadly configurable. It can act as a master, a slave, or both. It can further function as a protocol analyzer, performing protocol checks and calculating functional coverage.

The VIP package comes complete with everything needed for UVM verification against the I2C spec using the Questa or VCS simulators.

Deliverables include the compiled source code of the Verification IP; Verification Testbenches that can be used with the IP core and user’s SoC verification environment; and built-in Coverage Metrics that allow the user to readily determine the actual protocol coverage.

Support

The I2C-VIP as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available

Deliverables

 

 

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