- Supports latest specification: Philips/NXP Standard Version 1 through Version 6 (April 2014)
- Delivered pre-configured and set up for immediate use with the
- I2C-SMBUS Controller Core
- Language: System Verilog
- Methodology Support:
- UVM v1.1d
- Simulators supported:
- Mentor Questa® Advanced Simulator
- Synopsys VCS®
I2C Verification Features
- Multiple Agents:
supports both multi-master and multi-slave configurations
- General Call support
- Standard Mode support
- Read Request support
- Multi-byte read/write support
- Slave Response Control:
Implements user control of slave response fields such as data, slave busy, slave sending NACK, etc.
- I2C Timing Parameters
- I2C Master/Slave Address
I2C-VIPI2C Bus Master/Slave Verification IP
The I2C-VIP verification IP package makes verification of an I2C bus controller easier and more complete, and it comes ready for immediate use with the I2C Bus Controller IP core from CAST.
The I2C-VIP supports the latest iteration of the Inter-Integrated Circuit standard—NXP Version 6 (April 2014)—and the popular UVM verification methodology.
The I2C-VIP is highly flexible and broadly configurable. It can act as a master, a slave, or both. It can further function as a protocol analyzer, performing protocol checks and calculating functional coverage.
The VIP package comes complete with everything needed for UVM verification against the I2C spec using the Questa or VCS simulators.
Deliverables include the compiled source code of the Verification IP; Verification Testbenches that can be used with the IP core and user’s SoC verification environment; and built-in Coverage Metrics that allow the user to readily determine the actual protocol coverage.
The I2C-VIP as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available
- I2C Master/Slave UVM Verification IP (System Verilog)
- Test cases to exercise all I2C features
- Built-in coverage analysis model
- Sample UVM ScoreBoard
- RTL Verilog I2C DUT
- VIP User Guide