ECP IP Core ECP_SLAVE Triple Extended Capabilities Parallel Port Slave Core

Implements an Extended Capabilities parallel Port (ECP) that makes a peripheral compliant with the IEEE1284-2000 specification.

The ECP is an asynchronous, byte-wide, bidirectional channel between a peripheral and a host computer. The ECP_Slave core implements the fast ECP mode, and also the forward Compatibility and reverse Nibble modes (useful together for bidirectional support of older devices). It supports Device ID strings in the Nibble and ECP modes, thus permitting the identification of the peripheral on Plug & Play operating systems.

The core also implements run length encoding (RLE) decompression on ECP forward direction transfers, providing real-time data compression ratios up to 64:1 and especially useful for transferring raster images with long strings of identical data.

The ECP_Slave core has been developed for reuse in ASICs and FPGAs and is a fully synchronous design. It has one global clock domain, no latches, and tristate enable signals are provided to combine input and output buses to a single bi-directional bus.

See representative implementation results (each in a new pop-up window):

Applications

The ECP_Slave core is ideal for applications that need a bi-directional connection to a PC at medium data transfer rates, with low complexity and low development cost. Examples include:

• Printers, Scanners, Multifunction Devices
• Experimental devices
• Instruments
• Data acquisition systems

Symbol Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• A Software Development Kit for Win2000/XP operating systems
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including everything needed to test the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

 

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Functional Description | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx