CAN IP Core CAN-CTRL Flexible CAN 2.0 Bus Controller Core

Implements a CAN protocol bus controller that performs serial communication according to the CAN 2.0A and 2.0B specifications.

The CAN protocol uses a multi-master bus configuration for the transfer of frames between nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up economic and reliable links between various components. It appears as a memory-mapped I/O device to the host processor, which accesses the CAN core to control the transmission or reception of frames.

The CAN core is easy to use and integrate. featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA-APB interface. It implements a flexible buffering scheme, allowing fine-tuning of the core size to the requirements of each specific application. The number of receive buffers is synthesis-time configurable from 2 to 31. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). The PTB can store one message, while the number of included buffer slots for the STB is synthesis-time configurable 0 to 16 slots.

The core Implements functionality similar to the Philips SJA1000 working with its PeliCAN mode extensions, providing error analysis, diagnosis, system maintenance and optimization features.

The CAN core is robustly verified and proven in multiple production designs.

See representative implementation results (each in a new pop-up window):

Applications

The CAN-CTRL core can be integrated in devices that use CAN or higher-layer, CAN-based communication protocols. Apart from automotive, such devices are used in industrial (e.g. devices implementing the CANopen and DeviceNet protocols), aviation (e,g. devices implementing the ARINC-825 and CANaerospace protocols), marine (e.g. devices implementing the NMEA 2000 protocol) and other applications.

Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been certified by a Bosch reference model and has been production proven multiple times.

Deliverables

The core includes everything required for successful implementation:

• VHDL or Verilog RTL source code
• Post-synthesis EDIF (netlist licenses)
• Testbenches
• Behavioral tests
• Bosch reference model
• Post-synthesis verification
• Simulation scripts
• Synthesis scripts
• Documentation