CAN Specifications Support
- CAN 2.0 & CAN-FD (ISO 11898-1.2015, plus earlier ISO and Bosch specifications)
- TTCAN (ISO 11898-4 level 1)
- Optimized for AUTOSAR and SAE J1939
- Error Analysis features enabling diagnostics, system maintenance, and system optimization
- Last error type
- Arbitration lost position
- Error Warning Limit
- Listen-Only Mode enables CAN bus traffic analysis and automatic bit-rate detection
- Loop back mode for self-testing
- Time-stamping support, compliant to CiA's 603 specification
Flexible Message Buffering and Filtering
- Configurable number of:
- receive buffers
- lower-priority transmit buffers
- independently programmable acceptance filters, 1 to 16
- One high-priority transmit buffer
- FIFO or priority mode for transmit buffers
Easy to Use and Integrate
- Programmable data rate up to 1 Mbit/s with CAN 2.0 and several Mbit/s with CAN FD option
- Programmable baud rate prescaler: 1 up to 1/256
- Single Shot Transmission Mode for lower software overhead and fast reloading of transmit buffer
- Programmable interrupt sources
- Generic 8-bit host-controller interface and optional 32-bit AMBA-APB or 32-bit AHB-Lite
Safety-Enhanced Version (optional)
- Certified ISO-26262 ASIL-B Ready
- ISO-26262 ASIL-C on request
- Implements ECC for SRAM and spatial redundancy for inner logic protection
- Compatible with any CAN2.0 transceiver (PHY) that supports ISO-11898, and various CAN-FD PHYs from NXP, MicroChip, OnSemi, Infineon, etc.
- Multiple times production proven
Call or click.
- General Product Brief
- Microsemi Product Brief
- Intel Product Brief
- Lattice Product Brief
- Xilinx Product Brief
- 10/04/19, CAN to TSN Gateway from CAST Bridges CAN 2.0/FD Buses with Time Sensitive Ethernet
- 09/20/19, CAST CAN 2.0/FD Bus IP is Safety-Ready with ISO 26262 Certification
- CAN in Automation Knowledge Pages
- CAN Bit Time Calculation with Calculator
- Ways to Transition from Classic CAN to the improved CAN FD (PDF)
- AE J1939 Standards collection
- AUTOSAR official web site
The configuration of the core you have provided fit perfectly with our requirements so we decided to use it as is without any modification.
Overall, I think that the core's performance was excellent, while the detailed documentation contributed a lot to the fast integration of the core into our system.“
— Nikos Vassiliadis, Electronics Engineer, Theon Sensors
CAST is a member of the CAN in Automation (CiA) user's and amnufacturer's trade group.
CAN-CTRLCAN 2.0 & CAN FD Bus Controller Core
Implements a CAN protocol bus controller that performs serial communication according to CAN 2.0, and CAN FD specifications. It supports the original Bosch protocol and ISO specifications as defined in ISO 1989—including time-triggered operation (TTCAN) as specified in ISO 19898-4—and is also optimized to support the popular AUTOSAR and SAE J1939 specifications.
The CAN protocol uses a multi-master bus configuration for the transfer of frames between nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up economic and reliable links between various components. It appears as a memory-mapped I/O device to the host processor, which accesses the CAN core to control the transmission or reception of frames.
The CAN core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application.
The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). The PTB can store one message, while the number of included buffer slots for the STB is synthesis-time configurable 0 to 16 slots.
The core implements functionality similar to the Philips SJA1000 working with its PeliCAN mode extensions, providing error analysis, diagnosis, system maintenance, and optimization features.
The CAN-CTRL is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The deliverables for this version include a Safety Manual (SAM), a Failure Modes, Effects and Diagnostics Analysis (FMEDA), and the ISO-26262 ASIL-B Ready certificate, issued by SGS-TÜV Saar GmbH. An ASIL-C compatible version can be made available and undergo certification upon request.
The CAN core is extensively verified and proven in multiple production designs. CAN bus verification IP (VIP) is also available for this core, for comprehensive verification of the core and its function within a system.
A 30-day free license for the
CAN-Xactor Verification IP is included
with each CAN-CTRL Controller Core delivery.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
The CAN-CTRL core can be integrated in devices that use CAN or higher-layer, CAN-based communication protocols. In addition to traditional automotive applications, such devices are used in industrial (e.g. the CANopen and DeviceNet protocols), aviation (e,g. the ARINC-825 and CANaerospace protocols), marine (e.g. the NMEA 2000 protocol) and other applications.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core has been rigorously verified and has been production proven multiple times.
The core includes everything required for successful implementation:
- VHDL or Verilog RTL source code
- Post-synthesis EDIF (netlist licenses)
- Behavioral tests
- Post-synthesis verification
- Simulation scripts
- Synthesis scripts
- Linux driver
- 30-day free license to CAN-Xactor Verification IP