Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

CAN Specifications Support

  • CAN 2.0 & CAN-FD (ISO 11898-1.2015, plus earlier ISO and Bosch specifications)
  • TTCAN (ISO 11898-4 level 1)
  • Optimized for AUTOSAR and SAE J1939

Enhanced Functionality

  • Error Analysis features enabling diagnostics, system maintenance, and system optimization
    • Last error type
    • Arbitration lost position
    • Error Warning Limit
  • Listen-Only Mode enables CAN bus traffic analysis and automatic bit-rate detection
  • Loop back mode for self-testing
  • Optional ECC memories support

Flexible Message Buffering and Filtering

  • Configurable number of receive buffers
  • One high-priority transmit buffer
  • Configurable number of lower-priority transmit buffers
  • FIFO or priority mode for transmit buffers
  • Configurable number of independently programmable 29-bit acceptance filters, 1 to 16

Easy to Use and Integrate

  • Programmable data rate up to 1 Mbit/s with CAN 2.0 and several Mbit/s with CAN FD option
  • Programmable baud rate prescaler: 1 up to 1/256
  • Single Shot Transmission Mode for lower software overhead and fast reloading of transmit buffer
  • Programmable interrupt sources
  • Generic 8-bit host-controller interface and optional 32-bit AMBA-APB or 32-bit AHB-Lite
  • A single host can control multiple CAN bus nodes via an optional Multi-CAN wrapper

Zero Risk

  • Link to commercial bus drivers (e.g. PCA82C250T by Philips)
  • Multiple times production proven

Efficient and Portable Design

  • Available in RTL, and portable to ASIC and FPGA technologies
  • Size of approximately 12,000 gates.

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Related Products

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Resources

Customer Comment

Theon Sensors' night vision system uses the CAN Bus Controller IP core from CAST, Inc."The CAST CAN core has been successfully integrated into our new night vision camera product which have been already shipped to one of our customers.

The configuration of the core you have provided fit perfectly with our requirements so we decided to use it as is without any modification.

Overall, I think that the core's performance was excellent, while the detailed documentation contributed a lot to the fast integration of the core into our system.“
— Nikos Vassiliadis, Electronics Engineer, Theon Sensors

Partnerships

CAST is a member of the CAN in Automation (CiA) user's and amnufacturer's trade group.

CAN-CTRLCAN 2.0 & CAN FD Bus Controller Core

Implements a CAN protocol bus controller that performs serial communication according to CAN 2.0, and CAN FD specifications. It supports the original Bosch protocol and ISO specifications as defined in ISO 1989—including time-triggered operation (TTCAN) as specified in ISO 19898-4—and is also optimized to support the popular AUTOSAR and SAE J1939 specifications.

The CAN protocol uses a multi-master bus configuration for the transfer of frames between nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up economic and reliable links between various components. It appears as a memory-mapped I/O device to the host processor, which accesses the CAN core to control the transmission or reception of frames.

The CAN core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application.

The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). The PTB can store one message, while the number of included buffer slots for the STB is synthesis-time configurable 0 to 16 slots. An optional wrapper instantiating multiple CAN controller cores easies integration in cases where multiple bus-nodes need to be controlled by the same host processor.

The core implements functionality similar to the Philips SJA1000 working with its PeliCAN mode extensions, providing error analysis, diagnosis, system maintenance, and optimization features.

CAN bus verification IP (VIP) is availableThe CAN core is extensively verified and proven in multiple production designs. CAN bus verification IP (VIP) is also available for this core, for comprehensive verification of the core and its function within a system.

See representative implementation results (each in a new pop-up window):

PCIe core ASIC numbers Microsemi numbers Altera numbers Lattice numbers Xilinx numbers

Applications

The CAN-CTRL core can be integrated in devices that use CAN or higher-layer, CAN-based communication protocols. In addition to traditional automotive applications, such devices are used in industrial (e.g. the CANopen and DeviceNet protocols), aviation (e,g. the ARINC-825 and CANaerospace protocols), marine (e.g. the NMEA 2000 protocol) and other applications.

Block Diagram

can-ctrl block diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been rigorously verified and has been production proven multiple times.

Deliverables

The core includes everything required for successful implementation:

 

 

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