Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

CAN Specifications Support

  • CAN 2.0 & CAN-FD (ISO 11898-1.2015, plus earlier ISO and Bosch specifications)
  • Time-Triggered TTCAN (ISO 11898-4 level 1)

CAN Node Bus Functional Model (BFM)

  • Transmitter and Receiver modes
  • Performs integration steps
  • Random configuration
    • Node type, bit timing rate, time base, jitter
  • Frame class models all frame formats and types
  • Timing class models all timing parameters (randomize, modifiable)
    • Multiple bit rates
    • Inter-frame delay
    • Bit phase delay adjustment
  • APIs to preload and access sparse memory regions
  • Error detection
    • callback,
    • bit stuffing and injection
  • Error injection/callbacks

Compliance Testsuite

  • Avery and Bosch compliance testsuites
  • Compliance checklist focused testing
    • ISO 16845 Conformance Testsuite
    • Avery-based Directed and Constrained random tests
    • Bosch VHDL Reference Model Test Plan
      – Basic compliance testsuite
      – Bosch VHDL reference model compliance

Contact Sales
Call or click.
+1 201.391.8300

Related Products

  • CAN-CTRL CAN 2.0 & CAN FD Bus Controller Core
  • CANFD-RD CAN 2.0 & CAN FD Reference Design

News Releases

 

Partnerships

CAST is a member of the CAN in Automation (CiA) user's and amnufacturer's trade group.

CAN-XactorVerification IP for the CAN 2.0 & CAN FD Bus Controller Core

CAN-Xactor is a comprehensive VIP package for CAN 2.0 and FD bus controllers. SoC and IP designers this CAN VIP package to ensure complete verification of their designs and full protocol and timing compliance.

CAN-Xactor implements a ready-to-use set of models, protocol checkers, and compliance testsuites in 100% native SystemVerilog and UVM. It supports the latest relevant specifications, including CAN 2.0 Part A/B and FD modes and Time-Triggered CAN.

Verification IP for the CAN Bus ConrollerThe complete bus functional CAN node model in the VIP package supports integration steps, transmitter and receiver modes (including multiple bit rates), inter-frame delay, and bit phase delay adjustment. It supports the random configuration of node type and bit timing rate, and includes APIs to preload and access sparse memory regions.

The BFM's frame class models all supported CAN frame formats and types. Its open and unencrypted timing class models all applicable timing parameters, including randomize and modifiable. The BFM also performs error detection (callback, bit stuffing) and injection.

The testsuites included with CAN-Xactor include both Avery-developed directed and constrained random tests and the full Bosch VHDL Reference Model test Plan.

Programming The Model

Controlling and executing the CAN bus model is straightforward, as shown in these examples.


  

Protocol Analyzer Trackers

An included tracker log monitors all levels and improves debug. It records both state transitions and comand-response sequences, as show in this example.

Support

The VIP as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The CAN VIP package includes everything required for successful verification:

 

 

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