CAN-CTRL Core — XILINX FPGA Results

The CAN-CTRL can be mapped to any Xilinx FPGA device (provided sufficient silicon resources are available).  The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include priority mode, TTCAN and CiA603 timestamping). Please contact CAST to get characterization data for your target configuration and technology.

Family Device CAN 2.0 CAN-FD
Logic Memory Logic Memory

Artix-7

XC7A15T

1,616 LUTs

511 Slices

1,088 bits
1 RAMB36

1,952 LUTs

652 Slices

4,224 bits
1 RAMB36

Virtex-7

XCVX300T

1,612 LUTs

522 Slices

1,942 LUs

646 Slices

Kintex UltraScale

XCKU060

1,595 LUTs

240 CLBs

1,937 LUTs

296 CLBs

Kintex UltraScale+

XKU15P

1590 LUTs

264 CLBs

1,941 LUTs

337 CLBs

Note: Host and CAN clock constrained to 80MHz

 

 

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