CAN-CTRL Core — ASIC Implementation Results

The CAN-CTRL can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include priority mode, TTCAN and CiA603 timestamping). Please contact CAST to get characterization data for your target configuration and technology.

Technology CAN 2.0 CAN-FD
Cell Area Memory Bits Cell Area Memory Bits
TSMC 65nm LP

14,700 um2

11,500 eq. Gates

1,088

18,000 um2

14,000 eq. Gates

4,224

TSMC 40nm G

7,350 um2

10,800 eq. Gates

8,800 um2

12,900 eq. Gates

TSMC 28nm HPC

4,380 um2

8,700 eq. Gates

5,260 um2

10.441 eq. Gates

Note: Host and CAN clock constrained to 200MHz

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