CAN-CTRL Core — Intel Implementation Results

The CAN-CTRL can be mapped to any Intel FPGA device (provided sufficient silicon resources are available).  The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include priority mode, TTCAN and CiA603 timestamping). Please contact CAST to get characterization data for your target configuration and technology.

Family Device CAN 2.0 CAN-FD
Logic Memory Logic Memory

Max 10

10M50

2,343 LEs

0 MULTs

1,088 bits
3 RAM Blocks

2,806 LEs

0 MULTs

4,224 bits

3 RAM Blocks

Cyclone V

5CEFA7

1,094 ALMs

1 DSP

1,325 ALMs

1 DSP

Cyclone 10 LP

10CL120

2,331 LEs

0 MULTs

2,808 LEs

0 MULTs

Cyclone 10 GX

10AX115

1,072 ALMs

1 DSP

1,317 ALMs

1 DSP

Arria V GX

5AGXBB3

1,092 ALMs

1 DSP

1,217 ALMs

1 DSP

Arria 10 GX

10AX115

1,117 ALMs

1 DSP

1,333 ALMs

1 DSP

Note: Host and CAN clock constrained to 80MHz

 

close window