Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.
   Stack

IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Subsystem suitable for the implementation of bridges or nodes for automotive or industrial Ethernet; integrates three IP cores:

IEEE 802.1AS Hardware Stack

  • Autonomously synchronizes internal Real-Time Clock to Grandmaster’s time
  • Returns timestamps to the system using absolute time
  • Provides periodic event triggers and alarm to assert host interrupt at specified absolute time
  • Automatically calculates point-to-point latency
  • Supports optional timer precision improvement by the host
  • Supports full-duplex, point-to-point links 
  • Supports time-aware end-points – not Grandmaster capable

IEEE 802.1Qav and 802.1Qbv Hardware Stack

  • Supports up to 8 traffic classes, as per VLAN (IEEE 802.1Q)
  • Enables bandwidth reservation and allocation per traffic class, and deterministic, low-latency, low-jitter communication for all traffic classes (IEEE 802.1Qav and IEEE 802.1Qbv)

Low-Latency Ethernet MAC

  • Enables high-precision synchronization in TSN networks
    • Egress latency: 10 Tx clock cycles
    • Ingress latency: 6 Rx clock  cycles
  • 10/100/1000 Mbit/s Ethernet and MII, GMII and RGMIII PHY interfaces

Easy System Integration

  • Autonomous operation, requires no host assistance once programmed
  • AMBA/AXI4 or Avalon Interfaces
    • AX4-Lite host interfaces, and AXI4-Stream for packet data
    • Avalon-MM host interface and Avalon-St for packet-data
  • Complete reference designs available for Altera and Xilinx, including sample application software

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

News Releases

TSN_CTRLTSN Ethernet Subsystem

The TSN_CTRL implements a configurable subsystem meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), and a low-latency Ethernet MAC.

IEEE802.1AS compliant AVB/TSN stack is part of the line of automitive IP cores from CAST, Inc.The subsystem is designed to enable high-precision timing synchronization and flexible yet accurate TSN traffic scheduling. Requiring no software assistance for its operation, it features minimal and deterministic ingress and egress latencies, and simplifies the development of time-aware applications.

While operating autonomously, the TSN_CTRL provides the system with timing information (time-stamps, alarms, etc.) that is typically required for the operation of a TSN network bridge or node. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements.

The TSN_CTRL uses standard AMBA® or Avalon® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide AXI4-Lite or Avalon-MM bus, and packet data are input and output via AXI-Streaming or Avalon ST interfaces with 8-bit data buses. 

The TSN_CTRL subsystem is designed with industry best practices, and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.

Options

The TSN_CTRL can be modified to meet the requirements of different applications in the following ways:

Applications

The TSN_CTRL is suitable for the implementation of sources of traffic and bridges for TSN Ethernet networks requiring robust, low-latency, and deterministic communication. Such networks are used in automotive, industrial control, and aerospace applications.

Block Diagram

TSN_CTRL block diagram

Support

The subsystem as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The subsystem has been rigorously verified, hardware-validated and tested in real-life environments.

Deliverables

The subsystem includes everything required for successful implementation:

 

 

 

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