Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
Automotive Ethernet
TSN Endpoint Controller
CAN-to-TSN Gateway
LIN
LIN Bus Master/Slave
LIN Bus VIP
SENT/SAE J2716
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

  • Modular multi-port MAC and PHY models
      • MAC Control, Status, & Service Registers
      • MDIO support
      • MAC Service layer
    • PHY-level PCS/PMA layer models
      • 10/100M, 1/10/25/40/50/100/200/400 Gbps
      • Supports AUI, serdes interfaces
      • Multiple FECs
      • NRZ and PAM-4 signaling
      • Auto-negotiation
      • Link Training
      • Pause operation
      • Programmable inter-frame gap timing
    • Supports key TSN IEEE 802.1 and 802.3 specifications (see text)
      • Additional MAC Service layer features
      • Tagged Frames support
      • Priority-based Flow Control (PFC)
      • Enhanced Transmission Selection (ETS)
      • Data Center Bridging eXchange (DCBX)
    • SystemVerilog/UVM models and test-suites
    • Timing class to models clocking, skews, min/max timing
    • Runtime configurable architecture including speed, number of lanes, FEC, Alignment Marker Dist
    • Callbacks at all levels including error frame, length, SFD, FCS, IPG, FEC injection capabilities
    • MAC, PCS, FEC, and AN protocol tracker logs
    • Built-in protocol checkers and coverage reports
    • Performance metrics: effective line rate, active/pause modes
    • UNH-based Compliance testsuite targets exercising protocol checklist items
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    Related Products

    News Releases

    Latest White Paper

    • Time Sensitive Networking — An Introduction to TSN

      Time Sensitive Networking — An Introduction to TSN

      This white paper provides an introduction to Time-Sensitive Networking (TSN), an evolving set of IEEE standards that enable the transmission of real-time video and other time-sensitive data over Ethernet. TSN provides for low-latency transmission, time scheduling, and resource sharing, and is increasingly used for automotive buses and other demanding networking applications.

    See more White Paper blog posts >>>

    Blog Posts

    TSN-VIPTSN Ethernet Verification IP

    The TSN-VIP Ethernet Verification IP package provides a complete, simulation-based functional verification solution for design levels from the TSN-EP TSN Ethernet End Point Controller core through a complete SoC.

    TSN-VIP includes MAC and PHY models, protocol checking, and an optional compliance testsuite based on the UNH-IOL test specifications. Its integration with the ARM® Fast Model integration enables running the TSN-EP software stack in one fully integrated testbench.

    Block Diagram

    Specification Conformance

    The TSN-VIP package supports these key TSN IEEE 802.1 and 802.3 specifications:

    Support

    The VIP as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

    Deliverables

    The VIP includes everything required for successful implementation:

     

     

     

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