TSN-ES Core Xilinx FPGA Implementation Results

The TSN-SE can be mapped to any Xilinx FPGA device (provided sufficient silicon resources are available).  The FPGA resources requirements depend on the core configuration. The following are sample results for a small number of core configurations.  Please contact CAST to get characterization data for your target configuration and technology.

Family/Device Configuration* Logic

Memory

Kintex 7
XC7k325-2

64 Lookup Entries
16kB Ingress Mem
4 Traffic Classes
1k TC Queue Depth

64 Lookup Entries
16kB Ingress Mem
4 Traffic Classes
1k TC Queue Depth

30 RAMB36
22 RAMB36

Kintex 7
XC7k325-2

256 Lookup Entries
16kB Ingress Mem
4 Traffic Classes
1k TC Queue Depth

256 Lookup Entries
16kB Ingress Mem
4 Traffic Classes
1k TC Queue Depth

57 RAMB36
23 RAMB36

Kintex 7
XC7k325-2

256 Lookup Entries
16kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth

256 Lookup Entries
16kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth

64 RAMB36
31 RAMB36

Kintex UltraScale
XCKU035-1-c

256 Lookup Entries
16kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth

256 Lookup Entries
16kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth

64 RAMB36
31 RAMB36

Kintex UltraScale+
XCKU3P-1-I

256 Lookup Entries
16kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth

256 Lookup Entries
16kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth

64 RAMB36
31 RAMB36

* Partial list of configuration parameters

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