TSN-ES Core Intel FPGA Implementation Results

The TSN-SE can be mapped to any Intel FPGA device (provided sufficient silicon resources are available). The FPGA resources requirements depend on the core configuration. The following are sample results for a typical core configurations. Please contact CAST to get characteriza-tion data for your target configuration and technology.

Family/Device Configuration* Logic

Memory

Cyclone V
5CSEBA6U19C6

64 Lookup Entries
16kB Ingress Mem
8 Traffic Classes
1k TC Queue Depth

7,891 ALMs 827,376 bits

* Partial list of configuration parameters

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