Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

TSN Ethernet Switched Endpoint

  • Two Ethernet ports & one host processor port
  • Suitable for daisy-chained networks such as rings

Low Latency & Flexible Switching

  • Low-latency Layer-2 Cut-Through Switching
  • Run-tine switch configuration enables fast response to network changes
  • 802.1Q Tagged VLAN support
  • Port-based VLAN
  • Configurable VLAN-PCP to TSN-Queue Mapping (QoS by PCP)
  • Flexible VLAN and MAC forwarding & filtering
  • Configurable MAC lookup table for dynamic and static entries & automatic ageing table

TSN Features

  • Ready for IEEE 802.1as (light-weight software stack available)
  • Traffic shaping per IEEE 802.1Qav & IEEE 802.1Qbv with eight TSN Queues
  • Frame preemption per IEEE 802.1Qbu and IEEE 802.1Qbr (coming soon)

Easy System Integration

  • AMBA/AXI4 Interfaces
    • 32-bit APB for control/status regis-ters
    • 32-bit AXI4-Stream for packet data
  • GMII or RGMII, and MIDO Ethernet PHY interface per port
  • Requires minimal host assistance for its initialization
  • Complete reference designs available for Altera and Xilinx, including sample application software

Verification IP

  • The TSN-VIP Ethernet Verification IP package is available for this core

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

  • TSN-EP TSN Ethernet Endpoint Controller
  • CAN2TSN CAN-to-TSN Ethernet Gateway/Bridge
  • CAN-CTRL CAN 2.0 & CAN FD Bus Controller Core
  • VIP for easy, comprehensive, CAN Bus verificationCAN-Xactor Verification IP for the CAN 2.0 & CAN FD Bus Controller Core
  • CANFD-RD CAN 2.0 & CAN FD Reference Design
  • LIN LIN Bus Master/Slave Controller Core
  • CSENT SENT/SAE J2716 Controller Core

News Releases

Latest White Paper

  • Time Sensitive Networking — An Introduction to TSN

    Time Sensitive Networking — An Introduction to TSN

    This white paper provides an introduction to Time-Sensitive Networking (TSN), an evolving set of IEEE standards that enable the transmission of real-time video and other time-sensitive data over Ethernet. TSN provides for low-latency transmission, time scheduling, and resource sharing, and is increasingly used for automotive buses and other demanding networking applications.

See more White Paper blog posts >>>

Blog Posts

TSN-SETSN Ethernet Switched Endpoint Controller

The TSN-SE implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav and IEEE 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.1Qbr), and a low-latency Ethernet MAC.

The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. With cut-through switching and minimal buffering even at the Ethernet MAC level, the TSN-SE features extremely low and deterministic ingress and egress latencies, and simplifies the development of time-aware applications. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements, and provides the system with timing information (time-stamps, alarms, etc.) that is typically required for the operation of a TSN network bridge or endpoint.

The TSN-SE uses standard AMBA® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide APB bus, and packet data are input and output via AXI-Streaming interfaces with 32-bit data buses.

The TSN-SE is designed with industry best practices, and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.

This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):

Intel numbers Xilinx numbers

Applications

The TSN-SE is suitable for the implementation of TSN Ethernet Endpoints in daisy chained networks (e.g. ring topologies) requiring robust, low-latency, and deterministic communication. Such networks are used in automotive, industrial control, medical, and aerospace applications.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The TSN-SE has been rigorously verified, hardware-validated and tested in real-life environments.
Interoperability tested and verified within TSN plugfests organized by the Labs Network Industry 4.0 (LNI 4.0) association, and the Industrial Internet Consortium (IIC).

Deliverables

The core includes everything required for successful implementation:

 

 

tw    fbk    li    li    li
Top of Page