Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
Automotive Ethernet
TSN Endpoint Controller
CAN-to-TSN Gateway
LIN
LIN Bus Master/Slave
LIN Bus VIP
SENT/SAE J2716
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

Time Synchronization

  • Implements IEEE 802.1AS
  • Grandmaster or Slave functionality
  • Highly accurate synchronization. Accuracy is typically in the order of few tens ns.
  • Provides the system with timestamps, periodic event triggers and alarm

Traffic Shaping

  • Implements IEEE 802.1Qav and IEEE 802.1Qbv
  • Supports up to 8 traffic classes, as per VLAN (IEEE 802.1Q)
  • Enables bandwidth reservation and allocation per traffic class, and deterministic, low-latency, low-jitter communication for all traffic classes

Low-Latency Ethernet MAC

  • Enables high-precision synchronization in TSN networks
  • Egress latency:
    10 Tx clock cycles
  • Ingress latency:
    6 Rx clock cycles
  • 10/100/1000 Mbit/s Ethernet
  • PHY interfaces: MII, GMII and RGMIII

Easy System Integration

  • AMBA/AXI4 or Avalon Interfaces
  • AX4-Lite host interfaces, and AXI4-Stream for packet data
  • Avalon-MM host interface and Avalon-St for packet-data
  • Complete reference designs available for Altera and Xilinx, including sample application software
  • Requires minimal host assistance for its initialization

Verification IP

  • The TSN-VIP Ethernet Verification IP package is available for this core

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

  • TSN-VIP TSN Ethernet Verification IP
  • CAN2TSN CAN-to-TSN Ethernet Gateway/Bridge
  • CAN-CTRL CAN 2.0 & CAN FD Bus Controller Core
  • VIP for easy, comprehensive, CAN Bus verificationCAN-Xactor Verification IP for the CAN 2.0 & CAN FD Bus Controller Core
  • CANFD-RD CAN 2.0 & CAN FD Reference Design
  • LIN LIN Bus Master/Slave Controller Core
  • CSENT SENT/SAE J2716 Controller Core

News Releases

Latest White Paper

  • Time Sensitive Networking — An Introduction to TSN

    Time Sensitive Networking — An Introduction to TSN

    This white paper provides an introduction to Time-Sensitive Networking (TSN), an evolving set of IEEE standards that enable the transmission of real-time video and other time-sensitive data over Ethernet. TSN provides for low-latency transmission, time scheduling, and resource sharing, and is increasingly used for automotive buses and other demanding networking applications.

See more White Paper blog posts >>>

Blog Posts

TSN-EPTSN Ethernet Endpoint Controller

The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), and a low-latency Ethernet MAC.

The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. Requiring minimal software assistance for its initialization, it features extremely low and deterministic ingress and egress latencies, and simplifies the development of time-aware applications. While operating autonomously, the TSN-EP provides the system with timing information (time-stamps, alarms, etc.) that is typically required for the operation of a TSN network endpoint device. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements.

The TSN-EP uses standard AMBA® or Avalon® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide AXI4-Lite or Avalon-MM bus, and packet data are input and output via AXI-Streaming or Avalon ST interfaces with 8-bit data buses. 

The TSN-VIP TSN Ethernet Verification IP package is available for this core.

The TSN-EP is designed with industry best practices, and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.

Block Diagram

Applications

The TSN-EP is suitable for the implementation of sources of traffic and bridges for TSN Ethernet networks requiring robust, low-latency, and deterministic communication. Such networks are used in automotive, industrial control, and aerospace applications.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The TSN-EP has been rigorously verified, hardware-validated, and tested in real-life environments.

It has also been interoperability tested and verified within TSN plugfests organized by the Labs Network Industry 4.0 (LNI 4.0) association, and the Industrial Internet Consortium (IIC).

The TSN-VIP TSN Ethernet Verification IP package is also available, to help test the TSN-EP or an SoC containing it.

Deliverables

The core includes everything required for successful implementation:

 

 

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