IEEE802_1AS Core — XILINX FPGA Results

The IEEE802_1AS can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides indicative implementation results, when all core clocks are constrained to 125 MHz, which is sufficient for a 1Gbps throughput on each direction. These sample results do not represent minimum area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Techonoly Area Freq (MHz)
5.500 LUTs


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