CSENT Core — XILINX FPGA Results

The CSENT can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following are sample implementation results, which do not represent the highest speed or smallest area possible for the core and do not include the area for the implementation of the FIFOs. Please contact CAST to get characterization data for your target configuration and technology.

Configuration Target Technology Area Fmax
TX & RX no FIFO
Kintex7 / xc7k480t-3
781 Slice LUTs, 639 Slice Regs
361 MHz
TX only no FIFO
Kintex7 / xc7k480t-3
430 Slice LUTs, 316 Slice Regs
358 MHz
TX & RX no FIFO
Artix7 / xc7a200t-3
773 Slice LUTs, 637 Slice Regs
246 MHz
TX only no FIFO
Artix7 / xc7a200t-3
401 Slice LUTs, 316 Slice Regs
247 MHz
TX & RX no FIFO
Virtex7 / xc7vx330t-3
782 Slice LUTs, 637 Slice Regs
364 MHz
TX only no FIFO
Virtex7 / xc7vx330t-3
430 Slice LUTs, 316 Slice Regs
379 MHz
TX & RX no FIFO
US Kintex / xcku035-3
766 CLB LUTs, 638 CLB Regs
460 MHz
TX only no FIFO
US Kintex / xcku035-3
405 CLB LUTs, 316 CLB Regs
427 MHz
TX & RX no FIFO
US Virtex / xcvu095-3
798 CLB LUTs, 638 CLB Regs
472 MHz
TX only no FIFO
US Virtex / xcvu095-3
407 CLB LUTs, 319 CLB Regs
446 MHz

 

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