CSENT Core — ASIC Implementation Results

The CSENT can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following are sample implementation results, which do not represent the highest speed or smallest area possible for the core and do not include the area for the implementation of the FIFOs. Please contact CAST to get characterization data for your target configuration and technology.

Configuration Target Technology Area Fmax
Tx and Rx
TSMC 28hpm
2410 um2 / 4,850 Gates
1000 MHz
Tx only
TSMC 28hpm
1152 um2 / 2,300 Gates
1000 MHz

close window