CSENT Core — Intel Implementation Results

The CSENT can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following are sample implementation results, which do not represent the highest speed or smallest area possible for the core and do not include the area for the implementation of the FIFOs. Please contact CAST to get characterization data for your target configuration and technology.

Configuration Target Technology Area Fmax
TX & RX no FIFO
StartixV / 5sgxea9n3fc5c4
570 ALMs, 693 Regs
315 MHz
TX only no FIFO
StartixV / 5sgxea9n3fc5c4
275 ALMs, 351 Regs
339 MHz
TX & RX no FIFO
CyloneV / 5ceba9f31c7
571 ALMs, 697 Regs
162 MHz
TX only no FIFO
CyloneV / 5ceba9f31c7
279 ALMs, 351 Regs
185 MHz
TX & RX no FIFO
ArriaV / 5agxbb3d4f35c4
570 ALMs, 701 Regs
204 MHz
TX only no FIFO
ArriaV / 5agxbb3d4f35c4
280 ALMs, 352 Regs
247 MHz
TX & RX no FIFO
Arria10 / 10as057k2f35i2lg
593 ALMs, 688 Regs
365 MHz
TX only no FIFO
Arria10 / 10as057k2f35i2lg
284 ALMs, 349 Regs
401 MHz

 

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