Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv

• MPEG Transport Stream

JPEG Still & Motion

Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Octal/Quad/Dual/Single SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Master/Slave Controller
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security

Encryption Primitives
AES, Programmable
Key Expander
Single, Triple

Hash Functions
SHA-3 (Keccak)

CAN-to-TSN Gateway

  • Enables bidirectional communication between up to seven CAN ports and one Ether-net port
  • UDP Encapsulation of CAN messages
    • CAN2.0 and CAN FD messages
    • Timestamps per CAN message
    • UDP port number selects the CAN Bus node
    • Multiple CAN messages in one UDP frame for better utilization of Ethernet bandwidth
  • Less than 30µs latency

CAN Features

  • Programmable payload type (CAN 2.0 or CAN FD) and data rate per CAN node
  • Up to 16 programmable 29-bit acceptance filters per CAN node
  • Configurable number of receive buffers
  • One high-priority transmit buffer
  • Configurable number of lower-priority transmit buffers

Ethernet Features

  • IPv4 support without packet fragmentation
  • ARP support with IP Cache
  • ICMP support (Ping Reply)
  • UDP Support
  • UDP Port Filtering
  • UDP/IP Unicast, Multicast and Broadcast
  • DHCP support

TSN Ethernet Features

  • Time Synchronization
    • Supports gPTP/IEEE 802.1AS. Filters out PTP frames and forwards them to the system for further processing
    • RTC & hardware timestamps for transmission and reception
  • Traffic Shaping
    • Implements IEEE 802.1Qav (credit-based shaper) & IEEE 802.1Qbv (time aware scheduling)
    • Configurable up to 256 control list entries
    • 2-8 traffic classes (configurable)

Easy System Integration

  • Configuration & status registers accessible via an AXI4-Lite slave port
  • Sample gPTP stack over FreeRTOS
  • Complete FPGA reference designs available.

Contact Sales
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Downloads (PDFs)

Related Products

  • CAN-CTRL CAN 2.0 & CAN FD Bus Controller
  • TSN-EP TSN Ethernet Endpoint IP core
  • UDPIP-1G/10G UDP/IP Hardware Protocol Stack>
  • EMAC-1G Low-Latency 10/100/1000 Ethernet MAC IP core

  • LIN LIN Bus Master/Slave Controller Core
  • CSENT SENT/SAE J2716 Controller Core

News Releases

Latest White Paper

  • Time Sensitive Networking — An Introduction to TSN

    Time Sensitive Networking — An Introduction to TSN

    This white paper provides an introduction to Time-Sensitive Networking (TSN), an evolving set of IEEE standards that enable the transmission of real-time video and other time-sensitive data over Ethernet. TSN provides for low-latency transmission, time scheduling, and resource sharing, and is increasingly used for automotive buses and other demanding networking applications.

See more White Paper blog posts >>>

Blog Posts

CAN2TSNCAN-to-TSN Ethernet Gateway/Bridge

The CAN2TSN IP subsystem implements a CAN-to-TSN Ethernet gateway. It enables low-latency, bidirectional communication between up to seven CAN bus ports and one Time-Sensitive Networking Ethernet port. IEEE802.1AS compliant AVB/TSN stack is part of the line of automitive IP cores from CAST, Inc.

The CAN ports can be connected to the same or different CAN networks, and each is independently programmable with the payload type (CAN 2.0 or CANFD) and data rate. The Ethernet port is connected to a 10/100/1000 Mbit network, and supports gPTP/IEEE 802.1AS timing synchronization and traffic shaping according to the IEEE 802.1Qav and IEEE 802.1Qbv standards.

The CAN2TSN timestamps received CAN messages, encapsulates them to UDP frames, and transmits them over Ethernet. In the opposite direction, the CAN2TSN accepts UDP frames encapsulating CAN messages, and extracts and forwards each to one of the CAN ports for transmission.

Each CAN port is associated with a UDP destination port and represents a traffic class for traffic shaping purposes on the Ethernet side. The latency in both direc-tions, CAN to Ethernet and Ethernet to CAN, is extremely low (<30µs), making the gateway suitable for real-time control applications.

To simplify system integration, the CAN2TSN uses standard interfaces and requires minimal software assistance. It interfaces with the SoC via AMBA™ AXI4 buses. It connects to the Ethernet PHY via a standard MII, GMII, or RGMII interface, and to the external CAN transceivers via an industry-standard three-wire (Rx, Tx, STBY) in-terface. The gateway implements DHCP, ARP, ICMP, UDPIP, IEEE 802.1Qav, and IEEE 802.1Qbv with custom hardware; only part of the gPTP stack is implemented in software to allow easy adaptation to future versions of the timing synchronization protocol. The lightweight gPTP software stack runs under FreeRTOS, and can be easily ported to another real-time operating system.

The CAN2TSN is designed with industry best practices, and is available in synthe-sizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, testbench, and comprehensive documentation.


The CAN2TSN can be used in industrial control or automotive systems, where devic-es with CAN bus connectivity co-exist with devices with TSN Ethernet connectivity.

Block Diagram

CAN2TSN block diagram


The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first inter-action. Additional maintenance and support options are available.


The CAN2TSN has been rigorously verified, hardware-validated, and tested in real-life environments.

The subsystem was developed by integrating proven IP cores from CAST: the CAN controller, and the UDPIP hard-ware stack IP cores are hundreds of times production proven, and the TSN Ethernet End Node has been Interop-erability tested and verified at TSN plugfests organized by the Labs Network Industry 4.0 (LNI 4.0) association and the Industrial Internet Consortium (IIC).


The core includes everything required for successful im-plementation:


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