Scalado CAPS™ Compliance
- Integrates SpeedTags™ technology
JPEG Features
- Programmable Huffman Tables (two DC, two AC) and Programmable quantization tables (four)
- Up to four color components (optionally extendable to 255 components)
- Supports all possible scan configurations and all JPEG formats for input/output data
- Supports any image size up to 64k x 64k
Additional Image Processing Capabilities
- Motion JPEG encoding/decoding
- Rate-Control (optional)
Designed for Easy Integration
- Single clock per input sample for encoding
- Fully programmable through standard JPEG stream marker segments
- Automatic headers generation
- Automatic program-once encode-many operation
Designed for High Quality
- Robust verification environment includes bit-accurate software model
- Scan-ready design architecture
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AHB Compression Core Bus Bridge
Related Products
- JPEG-C Baseline JPEG Compression Codec
- JPEG-D Baseline JPEG Compression Decoder
- JPEG-E Baseline Compression JPEG Encoder
- JPEG-E-X Baseline/Extended Sequential 12-bit DICOM JPEG Encoder
- CCBB-AHB AHB Compression Core Bus Bridge – adds an AHB interface to the SVE-JPEG-E core
Related Information
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Technology Info
See the JPEG entry at Wikipedia.
JPEG IP Core SVE-JPEG-E Scalado SpeedView JPEG Encoder Core
The SVE-JPEG-E core implements a high-performance image encoder that produces SpeedView™ enabled JPEG data streams.
Integrating the SpeedTags™ technology the SVE-JPEG-E outputs compressed streams that are compatible with SpeedView™, a member of Scalado’s CAPS™ imaging suite which is focused on providing enhanced functionality to camera equipped mobile devices. CAPS™ compatibility combined with a hardware architecture being able to process more than 500MSamples/sec, makes the SVE-JPEG-E a unique solution for mutli-megapixel applications.
Furthermore, the SVE-JPEG-E can be configured to output streams compatible to baseline JPEG, or non-standard motion-JPEG streams. Finally the core can be enhanced with a bit-rate control block, which may benefit applications that have tight bandwidth constraints.
Designed for ease of integration the core includes FIFO-like pixel and stream input/output interfaces. The deliverables include a software bit-accurate model that facilitates system on chip verification.
See representative implementation results (each in a new pop-up window):
Applications
The high-performance SVE-JPEG-E core is suitable for camera equipped mobile devices, such as PDAs, and Camera phones.
Block Diagram
Support
The SVE-JPEG-E core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The SVE-JPEG-E core has been verified through extensive simulation and rigorous code coverage measurements. It has also been proven in FPGA technologies.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL (VHDL or Verilog) RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Synthesis script (ASICs) or place and route script (FPGAs)
- Simulation script, vectors and expected results
- Sophisticated HDL Testbench
- Software (C++) Bit-Accurate Model
- Comprehensive user documentation, including detailed specifications and a system integration guide
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