Scaler IP Core SCALER-P Polynomial Video Scaler Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables | FPGA Development & Evaluation Platform

Implements a video image scaler that uses a polynomial scaling algorithm to produce good quality enlarged or reduced images while using little silicon area and having modest processing requirements.

The proprietary scaling algorithm delivers results comparable to bicubic image scaling but uses approximately one-half of the silicon area, requiring just 30,000 ASIC gates.

Integrated non-linear processing further enhances detail by performing selective pixel sharpening. The core can downscale up to four times, and upscale up to 32 times the original image frame size.

The polynomial video image scaler core is available for ASICs or FPGAs, and includes a complete ‘C’ reference driver and fully documented API. The core has been FPGA-proven, and is available in an optional FPGA-based reference system that provides a complete development environment for evaluation and early software development.

See representative implementation results (each in a new pop-up window):

Features

High-Efficiency Video Image Scaling

• Real time image scaling
• 4X downscale
• 32X upscale
• Low silicon usage
• Nonlinear sharpening filter
• Variable scale factor with single pixel increments
• 24-bits and 30-bits per pixel support

Easy SoC Integration

• Zero CPU overhead after initial setup
• Complete HW / SW verification suite
• Low internal SRAM usage
• AMBA 2.0 – APB Control Interface
• Device driver and API in C

FPGA Development & Evaluation Platform

• 32-bit MCU based system
• Real time video input
• Includes the SCALER-F Image Scaler, DDR-2 system, and display controller
• DVI digital output

Applications

As a post-processing block or embedded within an image processing system, the core is a good match for applications requiring real-time, good-quality image resizing, especially on smaller screens and displays. It is best used with video rather than static images, e.g., as a video downscaler for picture-in-picture displays.

Block Diagram

Functional Description

The core includes standard interfaces for host CPU access and image data transfer.

An AMBA 2.0 Peripheral Bus (APB) slave interface is standard, providing low-complexity transfers of configuration information to the core. All internal configuration and status registers are accessible from the APB.

Input and output image data is transferred via a streaming interface with flow control. Flow control is managed via a ready/accept control signal pair that transfers two pixels of image data when both are valid. The core is completely pipelined and can be stalled as necessary to properly manage input and output rates.

Additional interfaces may also be available; contact CAST Sales.

Support

The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

Verification testing has been performed using a bottom-to-top methodology. Testing is first performed at the module level and progresses up to the system level.

Module-level testing for this core consists of generating both randomized and corner case (boundary value) conditions across a wide variety of resolutions.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
• Reference driver, driver, and real time video player in C
• Sophisticated HDL self-checking Testbench including HDL source files for block level and top level testing
• Simulation script, vectors, expected results, and comparison utility
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including a fully documented API, timing constrains summary document, and functional specification.

FPGA Development & Evaluation Platform

The FPGA Development & Evaluation Platform available with this core implemented in an FPGA allows quick and cost-effective evaluation and early software prototyping.

The ready-to-run platform includes a 32-bit host processor capable of running custom applications, DVI and other built-in interfaces, and a peripherals suite running a flash-based ROM monitor that loads at power-up.

The ROM monitor allows for the development and download of customer specific application code developed using GCC, enabling simultaneous hardware and software evaluation.

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables | FPGA Development & Evaluation Platform

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