- Motion-JPEG Video Compression
- Ultra-low, sub-frame latency
- No frame buffering, eliminates the need for external DRAM
- Quality equivalent to video compression for compression ratios up to 20:1
- RTP encapsulation according to RFC 2435
- Compressed stream decodable by compliant software decoders/viewers such as VLC
- Host interface via AXi4-Lite or processor-free UDP-controlled operation
- AXI4-ST bus for Video & Stream
- Integration with Video-In Controllers (e.g., DVI, HDMI, MIPI-CSI, or SDI)
- Integration with IP-based MAC controllers (e.g., Ethernet or 802.11 WiFi)
- Multiple video channels, different video preprocessing modules, or different compression algorithms
Call or click.
- JPEG-E-S Baseline JPEG Encoder Core
- JPEG-EX-S Baseline and Extended JPEG Encoder Core
- JPEG-EX-F Ultra-Fast Baseline and Extended JPEG Encoder Core
- JPEG-D-S Baseline and Extended JPEG Decoder Core
- JPEG-DX-S Low-Latency AVC/H.264 Baseline Profile Decoder Core
- JPEG-DX-F Ultra-Fast Baseline and Extended JPEG Decoder Core
- JPEG-LS-E JPEG-LS Compression Encoder Core
See the JPEG entry at Wikipedia.
See the Motion JPEG entry at Wikipedia.
MJPEGOIP-HDE Motion JPEG Over IP – HD Video Encoder Subsystem
This Video Over IP Subsystem employs JPEG compression and RTP/UDP/IP encapsulation to enable the rapid development of complete motion JPEG video streaming products. Hardware reference designs and customization services complete the solution.
The subsystem uses CAST’s JPEG-E-S, JPEG2RTP, and UDPIP IP cores. Flexible interfaces allow easy integration of video and network controllers; the cores’ AMBA® AXI4-Lite™ slave interfaces allow a host processor to access all control and status registers. An optional custom logic module allows standalone, processor-free operation and provides access to control and status registers via UDP packets. Video and stream data are transferred among the subsystem’s modules using AXI-Stream, making removing or adding modules straightforward.
The produced stream can be decoded using Motion JPEG-compatible software viewers (e.g. VLC).
The MJPEGOIP-HDE Subsystem is suitable for live streaming in broadcasting, surveillance, industrial, defense, and medical applications. The platform consumes significantly less energy than software-based solutions, making it ideal as a compression coprocessor in battery-operated devices with video streaming capabilities.
A turnkey reference design for Xilinx’s Kintex-7 FPGA KC705 Evaluation Kit is readily available. The reference design integrates the MJPEGOIP-HDE Subsystem with Xilinx’s Ethernet MAC, and uses an HDMI receiver daughter-card for video input.
|FPGA Family / Platform||
3rd Party Cores
|Xilinx Kintex-7 / KC705||HDMI (AES-FMC-IMAGEON-G card)||1G Ethernet||Xilinx TEMAC controller||720p25/30/50/60 & 1080p@30|
CAST can integrate the MJPEGOIP-HDE subsystem with your choice of video-in, and network controllers, and map it to Xilinx or Altera FPGA boards offering sufficient resources. We can also modify the subsystem to support multiple video channels, or different CAST compression cores.
JPEG Cores available from CAST
The MJPEGOIP-HDE is a member of the JPEG family of cores that CAST offers. The following table summarizes the family members and highlights their basic features.
|Extended Sequential JPEG|
|Motion JPEG Payload|
|Sub-sampling Formats||Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0|
|Image Resolution||16x16 to 64k x 64k|
|Max. Sample Depth||8||12||12||8||12||12|
|Raster Conversion||Included – Optionally Instantiated|
|Color Samples/Cycle||1||1||1 to 32||1||1||1 to 32|
|ASIC Area (eq. Gates)||70k||80k||120k1||65k||75k||110k1|
|Available in RTL Source Code|
|Available as targeted netlist|
|1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample|