Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.
   Stack

IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Complete subsystem streams 1080p video with lower latency, less power consumption, and fewer silicon re-sources than hardware video codecs or software compression.
  • Motion-JPEG Video Compression
    • Ultra-low, sub-frame latency capable
    • No frame buffering, eliminates the need for external DRAM
    • Quality equivalent to video compression for compression ratios up to 20:1
  • RTP encapsulation according to RFC 2435 
    • Compressed stream decodable by compliant software decoders/viewers such as VLC
  • Host interface via AXi4-Lite or processor-free UDP-controlled operation
  • AXI4-ST bus for Video & Stream

Customization Options

  • Integration with Video-In Controllers (e.g., DVI, HDMI, MIPI-CSI, or SDI)
  • Integration with IP-based MAC controllers (e.g., Ethernet or 802.11 WiFi)
  • Multiple video channels, different video preprocessing modules, or different compression algorithms

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

General Product Brief

Related Products

Compare
Versions

  • JPEG-E-S Baseline JPEG Encoder Core
  • JPEG-EX-S Baseline and Extended JPEG Encoder Core
  • JPEG-EX-F Ultra-Fast Baseline and Extended JPEG Encoder Core
  • JPEG-D-S Baseline and Extended JPEG Decoder Core
  • JPEG-DX-S Low-Latency AVC/H.264 Baseline Profile Decoder Core
  • JPEG-DX-F Ultra-Fast Baseline and Extended JPEG Decoder Core

News Releases

Articles

See the JPEG entry at Wikipedia.

See the  Motion JPEG entry  at Wikipedia.

Blog Posts

MJPEGOIP-HDE Motion JPEG Over IP – HD Video Encoder Subsystem

This Video Over IP Subsystem employs JPEG compression and RTP/UDP/IP encapsulation to enable the rapid development of complete motion JPEG video streaming products. Hardware reference designs and customization services complete the solution.

The subsystem uses CAST’s JPEG-E-S, JPEG2RTP, and UDPIP IP cores. Flexible interfaces allow easy integration of video and network controllers; the cores’ AMBA® AXI4-Lite™ slave interfaces allow a host processor to access all control and status registers. An optional custom logic module allows standalone, processor-free operation and provides access to control and status registers via UDP packets. Video and stream data are transferred among the subsystem’s modules using AXI-Stream, making removing or adding modules straightforward.  

The produced stream can be decoded using Motion JPEG-compatible software viewers (e.g. VLC).

Applications

The MJPEGOIP-HDE Subsystem is suitable for live streaming in broadcasting, surveillance, industrial, defense, and medical applications. The platform consumes significantly less energy than software-based solutions, making it ideal as a compression coprocessor in battery-operated devices with video streaming capabilities.

Block Diagram

MJPEGOIP-HDE Motion JPEG Over IP – HD Video Encoder Subsystem Block Diagram

Reference Designs

A turnkey reference design for Xilinx’s Kintex-7 FPGA KC705 Evaluation Kit is readily available. The reference design integrates the MJPEGOIP-HDE Subsystem with Xilinx’s Ethernet MAC, and uses an HDMI receiver daughter-card for video input.

FPGA Family /  Platform

Video-In

Stream Out

3rd Party Cores

Video Formats

Xilinx Kintex-7 / KC705 HDMI  (AES-FMC-IMAGEON-G card) 1G Ethernet Xilinx TEMAC controller 720p25/30/50/60 & 1080p@30

Customization Services

CAST can integrate the MJPEGOIP-HDE subsystem with your choice of video-in, and network controllers, and map it to Xilinx or Intel FPGA boards offering sufficient resources. We can also modify the subsystem to support multiple video channels, or different CAST compression cores.

JPEG Cores available from CAST

The MJPEGOIP-HDE is a member of the JPEG family of cores that CAST offers. The following table summarizes the family members and highlights their basic features.

  JPEG IP Cores JPEG-LS IP Cores

JPEG-E-S
Baseline
JPEG Encoder

JPEG-EX-S
Extended
JPEG Encoder

JPEG-EX-F
Ultra Fast Extended
JPEG Encoder

JPEG-D-S
Baseline
JPEG Decoder

JPEG-DX-S
Extended
JPEG Decoder

JPEG-DX-F
Ultra Fast Extended
JPEG Decoder

JPEG-LS-E
JPEG-LS Encoder

JPEG-LS-D
JPEG-LS Decoder

Function Encoder Decoder Encoder Decoder
Compression Type  Lossy Lossless/Lossy
Compression Standard JPEG — ISO/IEC 10918-1 JPEG-LS —  ISO/IEC 14495-1
Supported Standard Modes Baseline Sequential DCT Baseline Sequential DCT and Extended Sequential DCT Lossless& NEAR lossless Baseline Sequential DCT and Extended Sequential DCT Lossless & NEAR lossless
Motion JPEG Payload included included included included included included not supported not supported
Sub-sampling Formats Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0
Max. Image Resolution 64k x 64k 64k x 64k > 64k x 64k
Max. Sample Depth 8 12 12 8 12 12 16
Rate control included included included N/A N/A N/A N/A
Raster Conversion Included – Optionally Instantiated Included – Optionally Instantiated N/A
Color Samples/Cycle 1 1 1 to 32 1 1 1 to 32 1 to 32 1 to 32
ASIC Area  (eq. Gates) 70k 80k 120k1 65k 75k 110k1 40K2 40K2
Available in RTL Source Code not supported included included not supported included included included included
Available as targeted netlist included included included included included included included included

Notes:

1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample.

2) Silicon Resources for one sample/cycle configuration, and 8 bits per color sample.

 

 

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