CAST LJPEG-E Core — XILINX FPGA Results

Xilinx results using balanced area/speed constraints during synthesis and place and route, while assuming that all core I/Os are routed off-chip.

Xilinx Device Slices
 Fmax
(MHz)
 I/Os BRAM Special Features
 ISE
Spartan-3
3S1000-5		 2,041 90 131 2 RAMB16 - 12.2
Spartan-6
6SLX9-3		 1,101 120 131 2 RAMB16 - 12.2
Virtex-5
5VLX30-3		 617 190 131 2 RAMB36 - 12.2
Virtex-6
6VLX75T-3		 792 245 131 2 RAMB36 - 12.2

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